145 lines
7.0 KiB
Bash
Executable File
145 lines
7.0 KiB
Bash
Executable File
#!/bin/bash
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set -e
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source openfpga.sh
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PYTHON_EXEC=python3.8
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###############################################
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# OpenFPGA Shell with VPR8
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##############################################
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echo -e "FPGA-Verilog Feature Tests";
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echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
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run-task fpga_verilog/lut_design/single_mode --debug --show_thread_logs
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echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 ";
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run-task fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs
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echo -e "Testing Verilog generation for LUTs: fracturable LUT4 with embedded carry logic";
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run-task fpga_verilog/lut_design/frac_lut4_arith --debug --show_thread_logs
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echo -e "Testing Verilog generation for LUTs: native fracturable LUT4 ";
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run-task fpga_verilog/lut_design/frac_native_lut4 --debug --show_thread_logs
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echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes";
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run-task fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs
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echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 ";
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run-task fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs
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echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers";
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run-task fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs
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echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
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run-task fpga_verilog/untileable --debug --show_thread_logs
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echo -e "Testing Verilog generation with hard adder chain in CLBs ";
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run-task fpga_verilog/adder/hard_adder --debug --show_thread_logs
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echo -e "Testing Verilog generation with soft adder chain in CLBs ";
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run-task fpga_verilog/adder/soft_adder --debug --show_thread_logs
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echo -e "Testing Verilog generation with 1k block RAMs ";
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run-task fpga_verilog/bram/dpram1k --debug --show_thread_logs
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echo -e "Testing Verilog generation with 1k block RAMs spanning two columns ";
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run-task fpga_verilog/bram/wide_dpram1k --debug --show_thread_logs
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echo -e "Testing Verilog generation with heterogeneous fabric using 8-bit single-mode multipliers ";
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run-task fpga_verilog/dsp/single_mode_mult_8x8 --debug --show_thread_logs
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echo -e "Testing Verilog generation with heterogeneous fabric using 16-bit multi-mode multipliers ";
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run-task fpga_verilog/dsp/multi_mode_mult_16x16 --debug --show_thread_logs
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echo -e "Testing Verilog generation with heterogeneous fabric using multi-width 16-bit multi-mode multipliers ";
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run-task fpga_verilog/dsp/wide_multi_mode_mult_16x16 --debug --show_thread_logs
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echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
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run-task fpga_verilog/io/multi_io_capacity --debug --show_thread_logs
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echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
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run-task fpga_verilog/io/reduced_io --debug --show_thread_logs
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echo -e "Testing Verilog generation with embedded I/Os for an FPGA ";
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run-task fpga_verilog/io/embedded_io --debug --show_thread_logs
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echo -e "Testing Verilog generation with SoC I/Os for an FPGA ";
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run-task fpga_verilog/io/soc_io --debug --show_thread_logs
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echo -e "Testing Verilog generation with registerable I/Os for an FPGA ";
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run-task fpga_verilog/io/registerable_io --debug --show_thread_logs
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echo -e "Testing Verilog generation with adder chain across an FPGA";
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run-task fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs
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echo -e "Testing Verilog generation with shift register chain across an FPGA";
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run-task fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs
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echo -e "Testing Verilog generation with scan chain across an FPGA";
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run-task fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs
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echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure";
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run-task fpga_verilog/mux_design/tree_structure --debug --show_thread_logs
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echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2";
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run-task fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs
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echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders";
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run-task fpga_verilog/mux_design/local_encoder --debug --show_thread_logs
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echo -e "Testing Verilog generation with routing multiplexers without buffers";
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run-task fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs
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echo -e "Testing Verilog generation with routing multiplexers with input buffers only";
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run-task fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
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echo -e "Testing Verilog generation with routing multiplexers with output buffers only";
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run-task fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs
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echo -e "Testing Verilog generation with routing multiplexers with constant gnd input";
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run-task fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs
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echo -e "Testing Verilog generation with routing multiplexers without constant inputs";
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run-task fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
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echo -e "Testing Verilog generation with behavioral description";
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run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog --debug --show_thread_logs
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run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog_default_nettype_wire --debug --show_thread_logs
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echo -e "Testing synthesizable Verilog generation with external standard cells";
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run-task fpga_verilog/verilog_netlist_formats/synthesizable_verilog --debug --show_thread_logs
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echo -e "Testing implicit Verilog generation";
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run-task fpga_verilog/verilog_netlist_formats/implicit_verilog --debug --show_thread_logs
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run-task fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire --debug --show_thread_logs
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echo -e "Testing explicit Verilog generation";
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run-task fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire --debug --show_thread_logs
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echo -e "Testing Verilog generation with flatten routing modules";
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run-task fpga_verilog/flatten_routing --debug --show_thread_logs
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echo -e "Testing Verilog generation with duplicated grid output pins";
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run-task fpga_verilog/duplicated_grid_pin --debug --show_thread_logs
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echo -e "Testing Verilog generation with spy output pads";
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run-task fpga_verilog/spypad --debug --show_thread_logs
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echo -e "Testing Power-gating designs";
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run-task fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug
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echo -e "Testing Depopulated crossbar in local routing";
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run-task fpga_verilog/depopulate_crossbar --debug --show_thread_logs
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echo -e "Testing Fully connected output crossbar in local routing";
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run-task fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
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echo -e "Testing through channels in tileable routing";
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run-task fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
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run-task fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
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# Verify MCNC big20 benchmark suite with ModelSim
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# Please make sure you have ModelSim installed in the environment
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# Otherwise, it will fail
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#run-task fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20
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#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
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