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OpenFPGA
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OpenFPGA/fpga_flow/benchmarks/Verilog
History
Ganesh Gore 54f6ca2687 Added lattice benchmark settings 2019-07-01 11:07:23 -06:00
..
MCNC Path correction in tech debugging + correction of yosys rewrite file in fpga_flow 2019-05-30 09:52:19 -06:00
Test_Modes Add path modification in file changing a keyword into OpenFPGA full path 2019-06-04 15:21:15 -06:00
lattice_ultra_example Added lattice benchmark settings 2019-07-01 11:07:23 -06:00
.gitignore Added lattice benchmark settings 2019-07-01 11:07:23 -06:00