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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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99f5a86b49
OpenFPGA
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vpr
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tangxifan
e89d8e4493
bug fix for clock connection builder by supporting fake switch when adding edges to RRGraph object
2020-02-04 21:56:54 -07:00
..
scripts
add vpr8 libs and core engine for further integration
2020-01-03 16:14:42 -07:00
src
bug fix for clock connection builder by supporting fake switch when adding edges to RRGraph object
2020-02-04 21:56:54 -07:00
test
add vpr8 libs and core engine for further integration
2020-01-03 16:14:42 -07:00
CMakeLists.txt
move rr_graph back to vpr because the reader and writer requires too much dependency on the core engine
2020-01-31 15:42:44 -07:00
main.ui
add vpr8 libs and core engine for further integration
2020-01-03 16:14:42 -07:00
valgrind.supp
bring RRGraph object and writer online
2020-01-31 16:39:40 -07:00
vpr
add vpr8 libs and core engine for further integration
2020-01-03 16:14:42 -07:00