551 lines
16 KiB
C++
551 lines
16 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct EquivMakeWorker
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{
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Module *gold_mod, *gate_mod, *equiv_mod;
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pool<IdString> wire_names, cell_names;
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CellTypes ct;
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bool inames;
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vector<string> blacklists;
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vector<string> encfiles;
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pool<IdString> blacklist_names;
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dict<IdString, dict<Const, Const>> encdata;
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pool<SigBit> undriven_bits;
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SigMap assign_map;
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dict<SigBit, pool<Cell*>> bit2driven; // map: bit <--> and its driven cells
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CellTypes comb_ct;
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EquivMakeWorker()
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{
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comb_ct.setup_internals();
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comb_ct.setup_stdcells();
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}
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void read_blacklists()
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{
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for (auto fn : blacklists)
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{
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std::ifstream f(fn);
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if (f.fail())
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log_cmd_error("Can't open blacklist file '%s'!\n", fn.c_str());
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string line, token;
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while (std::getline(f, line)) {
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while (1) {
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token = next_token(line);
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if (token.empty())
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break;
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blacklist_names.insert(RTLIL::escape_id(token));
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}
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}
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}
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}
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void read_encfiles()
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{
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for (auto fn : encfiles)
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{
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std::ifstream f(fn);
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if (f.fail())
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log_cmd_error("Can't open encfile '%s'!\n", fn.c_str());
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dict<Const, Const> *ed = nullptr;
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string line, token;
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while (std::getline(f, line))
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{
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token = next_token(line);
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if (token.empty() || token[0] == '#')
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continue;
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if (token == ".fsm") {
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IdString modname = RTLIL::escape_id(next_token(line));
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IdString signame = RTLIL::escape_id(next_token(line));
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if (encdata.count(signame))
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log_cmd_error("Re-definition of signal '%s' in encfile '%s'!\n", signame.c_str(), fn.c_str());
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encdata[signame] = dict<Const, Const>();
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ed = &encdata[signame];
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continue;
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}
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if (token == ".map") {
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Const gold_bits = Const::from_string(next_token(line));
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Const gate_bits = Const::from_string(next_token(line));
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(*ed)[gold_bits] = gate_bits;
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continue;
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}
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log_cmd_error("Syntax error in encfile '%s'!\n", fn.c_str());
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}
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}
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}
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void copy_to_equiv()
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{
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Module *gold_clone = gold_mod->clone();
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Module *gate_clone = gate_mod->clone();
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for (auto it : gold_clone->wires().to_vector()) {
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if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
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wire_names.insert(it->name);
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gold_clone->rename(it, it->name.str() + "_gold");
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}
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for (auto it : gold_clone->cells().to_vector()) {
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if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
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cell_names.insert(it->name);
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gold_clone->rename(it, it->name.str() + "_gold");
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}
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for (auto it : gate_clone->wires().to_vector()) {
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if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
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wire_names.insert(it->name);
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gate_clone->rename(it, it->name.str() + "_gate");
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}
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for (auto it : gate_clone->cells().to_vector()) {
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if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
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cell_names.insert(it->name);
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gate_clone->rename(it, it->name.str() + "_gate");
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}
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gold_clone->cloneInto(equiv_mod);
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gate_clone->cloneInto(equiv_mod);
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delete gold_clone;
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delete gate_clone;
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}
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void find_same_wires()
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{
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SigMap assign_map(equiv_mod);
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SigMap rd_signal_map;
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// list of cells without added $equiv cells
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auto cells_list = equiv_mod->cells().to_vector();
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for (auto id : wire_names)
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{
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IdString gold_id = id.str() + "_gold";
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IdString gate_id = id.str() + "_gate";
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Wire *gold_wire = equiv_mod->wire(gold_id);
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Wire *gate_wire = equiv_mod->wire(gate_id);
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if (encdata.count(id))
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{
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log("Creating encoder/decoder for signal %s.\n", log_id(id));
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Wire *dec_wire = equiv_mod->addWire(id.str() + "_decoded", gold_wire->width);
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Wire *enc_wire = equiv_mod->addWire(id.str() + "_encoded", gate_wire->width);
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SigSpec dec_a, dec_b, dec_s;
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SigSpec enc_a, enc_b, enc_s;
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dec_a = SigSpec(State::Sx, dec_wire->width);
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enc_a = SigSpec(State::Sx, enc_wire->width);
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for (auto &it : encdata.at(id))
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{
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SigSpec dec_sig = gate_wire, dec_pat = it.second;
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SigSpec enc_sig = dec_wire, enc_pat = it.first;
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if (GetSize(dec_sig) != GetSize(dec_pat))
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log_error("Invalid pattern %s for signal %s of size %d!\n",
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log_signal(dec_pat), log_signal(dec_sig), GetSize(dec_sig));
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if (GetSize(enc_sig) != GetSize(enc_pat))
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log_error("Invalid pattern %s for signal %s of size %d!\n",
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log_signal(enc_pat), log_signal(enc_sig), GetSize(enc_sig));
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SigSpec reduced_dec_sig, reduced_dec_pat;
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for (int i = 0; i < GetSize(dec_sig); i++)
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if (dec_pat[i] == State::S0 || dec_pat[i] == State::S1) {
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reduced_dec_sig.append(dec_sig[i]);
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reduced_dec_pat.append(dec_pat[i]);
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}
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SigSpec reduced_enc_sig, reduced_enc_pat;
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for (int i = 0; i < GetSize(enc_sig); i++)
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if (enc_pat[i] == State::S0 || enc_pat[i] == State::S1) {
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reduced_enc_sig.append(enc_sig[i]);
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reduced_enc_pat.append(enc_pat[i]);
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}
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SigSpec dec_result = it.first;
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for (auto &bit : dec_result)
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if (bit != State::S1) bit = State::S0;
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SigSpec enc_result = it.second;
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for (auto &bit : enc_result)
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if (bit != State::S1) bit = State::S0;
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SigSpec dec_eq = equiv_mod->addWire(NEW_ID);
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SigSpec enc_eq = equiv_mod->addWire(NEW_ID);
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equiv_mod->addEq(NEW_ID, reduced_dec_sig, reduced_dec_pat, dec_eq);
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cells_list.push_back(equiv_mod->addEq(NEW_ID, reduced_enc_sig, reduced_enc_pat, enc_eq));
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dec_s.append(dec_eq);
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enc_s.append(enc_eq);
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dec_b.append(dec_result);
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enc_b.append(enc_result);
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}
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equiv_mod->addPmux(NEW_ID, dec_a, dec_b, dec_s, dec_wire);
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equiv_mod->addPmux(NEW_ID, enc_a, enc_b, enc_s, enc_wire);
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rd_signal_map.add(assign_map(gate_wire), enc_wire);
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gate_wire = dec_wire;
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}
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if (gold_wire == nullptr || gate_wire == nullptr || gold_wire->width != gate_wire->width) {
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if (gold_wire && gold_wire->port_id)
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log_error("Can't match gold port `%s' to a gate port.\n", log_id(gold_wire));
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if (gate_wire && gate_wire->port_id)
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log_error("Can't match gate port `%s' to a gold port.\n", log_id(gate_wire));
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continue;
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}
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log("Presumably equivalent wires: %s (%s), %s (%s) -> %s\n",
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log_id(gold_wire), log_signal(assign_map(gold_wire)),
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log_id(gate_wire), log_signal(assign_map(gate_wire)), log_id(id));
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if (gold_wire->port_output || gate_wire->port_output)
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{
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Wire *wire = equiv_mod->addWire(id, gold_wire->width);
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wire->port_output = true;
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gold_wire->port_input = false;
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gate_wire->port_input = false;
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gold_wire->port_output = false;
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gate_wire->port_output = false;
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for (int i = 0; i < wire->width; i++)
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equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
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rd_signal_map.add(assign_map(gold_wire), wire);
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rd_signal_map.add(assign_map(gate_wire), wire);
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}
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else
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if (gold_wire->port_input || gate_wire->port_input)
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{
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Wire *wire = equiv_mod->addWire(id, gold_wire->width);
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wire->port_input = true;
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gold_wire->port_input = false;
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gate_wire->port_input = false;
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equiv_mod->connect(gold_wire, wire);
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equiv_mod->connect(gate_wire, wire);
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}
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else
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{
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Wire *wire = equiv_mod->addWire(id, gold_wire->width);
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SigSpec rdmap_gold, rdmap_gate, rdmap_equiv;
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for (int i = 0; i < wire->width; i++) {
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if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) {
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log(" Skipping signal bit %s [%d]: undriven on gold side.\n", id2cstr(gold_wire->name), i);
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continue;
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}
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if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) {
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log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i);
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continue;
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}
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equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
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rdmap_gold.append(SigBit(gold_wire, i));
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rdmap_gate.append(SigBit(gate_wire, i));
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rdmap_equiv.append(SigBit(wire, i));
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}
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rd_signal_map.add(rdmap_gold, rdmap_equiv);
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rd_signal_map.add(rdmap_gate, rdmap_equiv);
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}
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}
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init_bit2driven();
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pool<Cell*> visited_cells;
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for (auto c : cells_list)
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for (auto &conn : c->connections())
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if (!ct.cell_output(c->type, conn.first)) {
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SigSpec old_sig = assign_map(conn.second);
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SigSpec new_sig = rd_signal_map(old_sig);
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if(old_sig != new_sig) {
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SigSpec tmp_sig = old_sig;
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for (int i = 0; i < GetSize(old_sig); i++) {
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SigBit old_bit = old_sig[i], new_bit = new_sig[i];
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visited_cells.clear();
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if (check_signal_in_fanout(visited_cells, old_bit, new_bit))
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continue;
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log("Changing input %s of cell %s (%s): %s -> %s\n",
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log_id(conn.first), log_id(c), log_id(c->type),
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log_signal(old_bit), log_signal(new_bit));
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tmp_sig[i] = new_bit;
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}
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c->setPort(conn.first, tmp_sig);
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}
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}
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equiv_mod->fixup_ports();
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}
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void find_same_cells()
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{
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SigMap assign_map(equiv_mod);
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for (auto id : cell_names)
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{
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IdString gold_id = id.str() + "_gold";
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IdString gate_id = id.str() + "_gate";
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Cell *gold_cell = equiv_mod->cell(gold_id);
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Cell *gate_cell = equiv_mod->cell(gate_id);
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if (gold_cell == nullptr || gate_cell == nullptr || gold_cell->type != gate_cell->type || !ct.cell_known(gold_cell->type) ||
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gold_cell->parameters != gate_cell->parameters || GetSize(gold_cell->connections()) != GetSize(gate_cell->connections()))
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try_next_cell_name:
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continue;
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for (auto gold_conn : gold_cell->connections())
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if (!gate_cell->connections().count(gold_conn.first))
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goto try_next_cell_name;
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log("Presumably equivalent cells: %s %s (%s) -> %s\n",
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log_id(gold_cell), log_id(gate_cell), log_id(gold_cell->type), log_id(id));
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for (auto gold_conn : gold_cell->connections())
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{
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SigSpec gold_sig = assign_map(gold_conn.second);
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SigSpec gate_sig = assign_map(gate_cell->getPort(gold_conn.first));
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if (ct.cell_output(gold_cell->type, gold_conn.first)) {
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equiv_mod->connect(gate_sig, gold_sig);
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continue;
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}
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for (int i = 0; i < GetSize(gold_sig); i++)
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if (gold_sig[i] != gate_sig[i]) {
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Wire *w = equiv_mod->addWire(NEW_ID);
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equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w);
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gold_sig[i] = w;
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}
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gold_cell->setPort(gold_conn.first, gold_sig);
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}
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equiv_mod->remove(gate_cell);
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equiv_mod->rename(gold_cell, id);
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}
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}
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void find_undriven_nets(bool mark)
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{
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undriven_bits.clear();
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assign_map.set(equiv_mod);
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for (auto wire : equiv_mod->wires()) {
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for (auto bit : assign_map(wire))
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if (bit.wire)
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undriven_bits.insert(bit);
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}
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for (auto wire : equiv_mod->wires()) {
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if (wire->port_input)
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for (auto bit : assign_map(wire))
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undriven_bits.erase(bit);
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}
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for (auto cell : equiv_mod->cells()) {
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for (auto &conn : cell->connections())
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if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first))
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for (auto bit : assign_map(conn.second))
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undriven_bits.erase(bit);
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}
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if (mark) {
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SigSpec undriven_sig(undriven_bits);
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undriven_sig.sort_and_unify();
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for (auto chunk : undriven_sig.chunks()) {
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log("Setting undriven nets to undef: %s\n", log_signal(chunk));
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equiv_mod->connect(chunk, SigSpec(State::Sx, chunk.width));
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}
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}
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}
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void init_bit2driven()
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{
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for (auto cell : equiv_mod->cells()) {
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if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_"))
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continue;
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for (auto &conn : cell->connections())
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{
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if (yosys_celltypes.cell_input(cell->type, conn.first))
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for (auto bit : assign_map(conn.second))
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{
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bit2driven[bit].insert(cell);
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}
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}
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}
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}
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bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigBit source_bit, SigBit target_bit)
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{
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if (source_bit == target_bit)
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return true;
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if (bit2driven.count(source_bit) == 0)
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return false;
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auto driven_cells = bit2driven.at(source_bit);
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for (auto driven_cell: driven_cells)
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{
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bool is_comb = comb_ct.cell_known(driven_cell->type);
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if (!is_comb)
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continue;
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if (visited_cells.count(driven_cell) > 0)
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continue;
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visited_cells.insert(driven_cell);
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for (auto &conn: driven_cell->connections())
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{
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if (yosys_celltypes.cell_input(driven_cell->type, conn.first))
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continue;
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for (auto bit: conn.second) {
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bool is_in_fanout = check_signal_in_fanout(visited_cells, bit, target_bit);
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if (is_in_fanout == true)
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return true;
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}
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}
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}
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return false;
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}
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void run()
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{
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copy_to_equiv();
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find_undriven_nets(false);
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find_same_wires();
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find_same_cells();
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find_undriven_nets(true);
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}
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};
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struct EquivMakePass : public Pass {
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EquivMakePass() : Pass("equiv_make", "prepare a circuit for equivalence checking") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" equiv_make [options] gold_module gate_module equiv_module\n");
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log("\n");
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log("This creates a module annotated with $equiv cells from two presumably\n");
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log("equivalent modules. Use commands such as 'equiv_simple' and 'equiv_status'\n");
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log("to work with the created equivalent checking module.\n");
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log("\n");
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log(" -inames\n");
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log(" Also match cells and wires with $... names.\n");
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log("\n");
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log(" -blacklist <file>\n");
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log(" Do not match cells or signals that match the names in the file.\n");
|
|
log("\n");
|
|
log(" -encfile <file>\n");
|
|
log(" Match FSM encodings using the description from the file.\n");
|
|
log(" See 'help fsm_recode' for details.\n");
|
|
log("\n");
|
|
log("Note: The circuit created by this command is not a miter (with something like\n");
|
|
log("a trigger output), but instead uses $equiv cells to encode the equivalence\n");
|
|
log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
|
{
|
|
EquivMakeWorker worker;
|
|
worker.ct.setup(design);
|
|
worker.inames = false;
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++)
|
|
{
|
|
if (args[argidx] == "-inames") {
|
|
worker.inames = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-blacklist" && argidx+1 < args.size()) {
|
|
worker.blacklists.push_back(args[++argidx]);
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-encfile" && argidx+1 < args.size()) {
|
|
worker.encfiles.push_back(args[++argidx]);
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (argidx+3 != args.size())
|
|
log_cmd_error("Invalid number of arguments.\n");
|
|
|
|
worker.gold_mod = design->module(RTLIL::escape_id(args[argidx]));
|
|
worker.gate_mod = design->module(RTLIL::escape_id(args[argidx+1]));
|
|
worker.equiv_mod = design->module(RTLIL::escape_id(args[argidx+2]));
|
|
|
|
if (worker.gold_mod == nullptr)
|
|
log_cmd_error("Can't find gold module %s.\n", args[argidx].c_str());
|
|
|
|
if (worker.gate_mod == nullptr)
|
|
log_cmd_error("Can't find gate module %s.\n", args[argidx+1].c_str());
|
|
|
|
if (worker.equiv_mod != nullptr)
|
|
log_cmd_error("Equiv module %s already exists.\n", args[argidx+2].c_str());
|
|
|
|
if (worker.gold_mod->has_memories() || worker.gold_mod->has_processes())
|
|
log_cmd_error("Gold module contains memories or procresses. Run 'memory' or 'proc' respectively.\n");
|
|
|
|
if (worker.gate_mod->has_memories() || worker.gate_mod->has_processes())
|
|
log_cmd_error("Gate module contains memories or procresses. Run 'memory' or 'proc' respectively.\n");
|
|
|
|
worker.read_blacklists();
|
|
worker.read_encfiles();
|
|
|
|
log_header(design, "Executing EQUIV_MAKE pass (creating equiv checking module).\n");
|
|
|
|
worker.equiv_mod = design->addModule(RTLIL::escape_id(args[argidx+2]));
|
|
worker.run();
|
|
}
|
|
} EquivMakePass;
|
|
|
|
PRIVATE_NAMESPACE_END
|