132 lines
3.8 KiB
C++
132 lines
3.8 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2014 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2014 Johann Glaser <Johann.Glaser@gmx.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct TraceMonitor : public RTLIL::Monitor
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{
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void notify_module_add(RTLIL::Module *module) YS_OVERRIDE
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{
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log("#TRACE# Module add: %s\n", log_id(module));
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}
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void notify_module_del(RTLIL::Module *module) YS_OVERRIDE
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{
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log("#TRACE# Module delete: %s\n", log_id(module));
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}
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void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE
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{
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log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig));
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}
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void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) YS_OVERRIDE
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{
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log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second));
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}
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void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) YS_OVERRIDE
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{
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log("#TRACE# New connections in module %s:\n", log_id(module));
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for (auto &sigsig : sigsig_vec)
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log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second));
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}
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void notify_blackout(RTLIL::Module *module) YS_OVERRIDE
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{
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log("#TRACE# Blackout in module %s:\n", log_id(module));
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}
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};
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struct TracePass : public Pass {
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TracePass() : Pass("trace", "redirect command output to file") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" trace cmd\n");
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log("\n");
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log("Execute the specified command, logging all changes the command performs on\n");
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log("the design in real time.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// .. parse options ..
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break;
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}
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TraceMonitor monitor;
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design->monitors.insert(&monitor);
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try {
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std::vector<std::string> new_args(args.begin() + argidx, args.end());
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Pass::call(design, new_args);
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} catch (...) {
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design->monitors.erase(&monitor);
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throw;
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}
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design->monitors.erase(&monitor);
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}
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} TracePass;
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struct DebugPass : public Pass {
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DebugPass() : Pass("debug", "run command with debug log messages enabled") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" debug cmd\n");
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log("\n");
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log("Execute the specified command with debug log messages enabled\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// .. parse options ..
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break;
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}
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log_force_debug++;
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try {
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std::vector<std::string> new_args(args.begin() + argidx, args.end());
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Pass::call(design, new_args);
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} catch (...) {
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log_force_debug--;
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throw;
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}
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log_force_debug--;
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}
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} DebugPass;
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PRIVATE_NAMESPACE_END
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