64 lines
1.8 KiB
Verilog
64 lines
1.8 KiB
Verilog
module test(
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input clk, wen,
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input [7:0] uns,
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input signed [7:0] a, b,
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input signed [23:0] c,
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input signed [2:0] sel,
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output [15:0] s, d, y, z, u, q, p, mul, div, mod, mux, And, Or, Xor, eq, neq, gt, lt, geq, leq, eqx, shr, sshr, shl, sshl, Land, Lor, Lnot, Not, Neg, pos, Andr, Orr, Xorr, Xnorr, Reduce_bool,
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output [7:0] PMux
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);
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//initial begin
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//$display("shr = %b", shr);
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//end
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assign s = a+{b[6:2], 2'b1};
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assign d = a-b;
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assign y = x;
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assign z[7:0] = s+d;
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assign z[15:8] = s-d;
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assign p = a & b | x;
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assign mul = a * b;
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assign div = a / b;
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assign mod = a % b;
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assign mux = x[0] ? a : b;
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assign And = a & b;
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assign Or = a | b;
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assign Xor = a ^ b;
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assign Not = ~a;
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assign Neg = -a;
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assign eq = a == b;
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assign neq = a != b;
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assign gt = a > b;
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assign lt = a < b;
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assign geq = a >= b;
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assign leq = a <= b;
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assign eqx = a === b;
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assign shr = a >> b; //0111111111000000
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assign sshr = a >>> b;
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assign shl = a << b;
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assign sshl = a <<< b;
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assign Land = a && b;
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assign Lor = a || b;
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assign Lnot = !a;
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assign pos = $signed(uns);
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assign Andr = &a;
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assign Orr = |a;
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assign Xorr = ^a;
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assign Xnorr = ~^a;
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always @*
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if(!a) begin
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Reduce_bool = a;
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end else begin
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Reduce_bool = b;
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end
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//always @(sel or c or a)
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// begin
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// case (sel)
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// 3'b000: PMux = a;
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// 3'b001: PMux = c[7:0];
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// 3'b010: PMux = c[15:8];
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// 3'b100: PMux = c[23:16];
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// endcase
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// end
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endmodule
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