50 lines
2.2 KiB
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50 lines
2.2 KiB
ReStructuredText
.. _openfpga_tools:
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Supported Tools
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---------------
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Internal Tools
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^^^^^^^^^^^^^^
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To enable various design purposes, OpenFPGA integrates several tools to i.e., FPGA-Verilog, FPGA-SDC and FPGA-bitstream (highlighted green in :ref:`fig_openfpga_tools`, with other popular open-source EDA tools, i.e., VPR and Yosys.
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.. _fig_openfpga_tools:
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.. figure:: figures/openfpga_tools.svg
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:width: 100%
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:alt: map to buried treasure
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OpenFPGA tool suites and design flows
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Third-Party Tools
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^^^^^^^^^^^^^^^^^
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OpenFPGA accepts and outputs in standard file formats, and therefore can
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interface a wide range of commercial and open-source tools.
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+--------------+-------------------------+---------------------+
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| Usage | Tools | Version Requirement |
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+==============+=========================+=====================+
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| Backend | Synopsys IC Compiler II | v2019.03 or later |
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| | Cadence Innovus | v19.1 or later |
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+--------------+-------------------------+---------------------+
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| Timing | Synopsys PrimeTime | v2019.03 or later |
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| Analyzer | | |
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| | Cadence Tempus | v19.15 or later |
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+--------------+-------------------------+---------------------+
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| Verification | Synopsys VCS | v2019.06 or later |
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| | Synopsys Formality | v2019.03 or later |
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| | Mentor ModelSim | v10.6 or later |
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| | Mentor QuestaSim | v2019.3 or later |
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| | Cadence NCSim | v15.2 or later |
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| | Icarus iVerilog | v10.1 or later |
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+--------------+-------------------------+---------------------+
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* The version requirements is based on our local tests. Older versions may work.
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