37 lines
698 B
Verilog
37 lines
698 B
Verilog
module DFFSRQ(SET,
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RST,
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CK,
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D,
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Q);
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//----- GLOBAL PORTS -----
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input [0:0] SET;
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//----- GLOBAL PORTS -----
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input [0:0] RST;
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//----- GLOBAL PORTS -----
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input [0:0] CK;
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//----- INPUT PORTS -----
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input [0:0] D;
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//----- OUTPUT PORTS -----
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output reg [0:0] Q;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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// ----- Internal logic should start here -----
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always @(posedge CK) begin
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if(RST) begin
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Q <= 1'b0;
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else if(SET) begin
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Q <= 1'b1;
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end else begin
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Q <= D;
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end
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end
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// ----- Internal logic should end here -----
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endmodule
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