OpenFPGA/yosys/tests/lut/check_map.ys

simplemap
equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/cmp2lut.v
design -load postopt
equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/gate2lut.v
design -load postopt
select -assert-count 0 t:* t:$lut %d