tangxifan 667c5f8944 [test] fixed a bug on the testcase		2023-07-27 22:02:28 -07:00
..
bottom_right_custom_pins/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
hetero_fabric_tile/config	[test] now heterogeneous testcases for tile modules pass	2023-07-27 20:30:32 -07:00
homo_fabric_tile/config	[test] fixed a bug on the testcase	2023-07-27 22:02:28 -07:00
homo_fabric_tile_2x2_preconfig/config	[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules	2023-07-27 17:03:02 -07:00
homo_fabric_tile_4x4_preconfig/config	[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules	2023-07-27 17:03:02 -07:00
homo_fabric_tile_adder_chain/config	[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules	2023-07-27 17:03:02 -07:00
homo_fabric_tile_clkntwk/config	[test] added a new test case to validate clock network when using the tile modules	2023-07-27 16:39:48 -07:00
homo_fabric_tile_global_tile_clock/config	[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules	2023-07-27 17:03:02 -07:00
homo_fabric_tile_preconfig/config	[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules	2023-07-27 17:03:02 -07:00
io_subtile/config	[test] now testcases are using proper arch	2023-05-03 21:47:21 +08:00
tileable_io/config	[test] now testcases are using proper arch	2023-05-03 21:47:21 +08:00
top_left_custom_pins/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
top_right_custom_pins/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00