tangxifan 90696def6d remove vpr Makefile		2019-06-07 23:44:39 -06:00
..
ARCH	Update spice path in architecture	2019-05-29 10:08:58 -06:00
Circuits	Add missing Verilog source, Archictecture folder and Testbenches correction	2019-05-13 16:41:35 -06:00
SRC	revert string to sprintf	2019-06-07 20:20:41 -06:00
SpiceNetlists	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
VerilogNetlists	fix path in regression test! TODO: must keep a duplicated copy for template.xml	2019-06-07 23:31:42 -06:00
CMakeLists.txt	Force graphics to false	2019-05-15 15:01:54 -06:00
go_fpga_spice.sh	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
go_fpga_verilog.sh	rename rr_switch_block to rr_gsb, a generic block	2019-06-06 17:41:01 -06:00
regression_verilog.sh	fix path in regression test! TODO: must keep a duplicated copy for template.xml	2019-06-07 23:31:42 -06:00