tangxifan b215b868c1 [HDL] Bug fix in HDL netlist due to port name mismatching		2021-02-01 11:35:25 -07:00
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adder.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
aib.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
dff.v	[HDL] Update dff netlist for SCFF used in configuration chain	2021-01-04 17:17:35 -07:00
dpram.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
dpram1k.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
dpram16k.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
frac_mem_32k.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
gpio.v	[HDL] Add new gpio cell with protection circuitry	2020-11-30 17:52:39 -07:00
latch.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
lut6.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
mult_32x32.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
mult_36x36.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
mux2.v	[HDL] Bug fix in HDL netlist due to port name mismatching	2021-02-01 11:35:25 -07:00
spram_4x1.v	Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)	2021-01-29 10:19:05 -07:00
sram.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00