| .. |
|
Buffer.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
FF.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
Inverter_1.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
Tapered_inverter.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
ccff_fpga.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
config_chain.svg
|
[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
|
2021-01-04 18:30:04 -07:00 |
|
config_chain_config_enable.svg
|
[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
|
2021-01-04 18:30:04 -07:00 |
|
config_chain_scan_capable.svg
|
[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
|
2021-01-04 18:30:04 -07:00 |
|
config_latch.png
|
update documentation about the frame-based configuration protocol
|
2020-06-11 19:31:11 -06:00 |
|
fabric_key_motivation.png
|
[Documentation] Update documentation about the multi-region configuration
|
2020-09-29 15:55:42 -06:00 |
|
frac_lut3_example.svg
|
[Doc] Patch the schematic of LUT circuit models to be consistent with netlists
|
2021-03-15 11:40:09 -06:00 |
|
frame_config_protocol.png
|
update documentation about the frame-based configuration protocol
|
2020-06-11 19:31:11 -06:00 |
|
frame_config_protocol_example.png
|
update documentation for standalone configuration protocol
|
2020-06-11 19:31:13 -06:00 |
|
full_adder_1bit_circuit_model.svg
|
[Doc] Add example circuit models for multipliers and update technical highlight with links to the examples
|
2021-05-24 15:24:50 -06:00 |
|
global_inout_ports.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
global_input_ports.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
global_tile_ports.png
|
[Doc] Add illustrative example to diff between global ports definitions
|
2020-11-12 09:24:39 -07:00 |
|
gpin_ports.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
gpio_ports.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
gpout_ports.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
iopad.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
lut_arith_example.svg
|
[Doc] Update documentation about the super LUT feature
|
2021-02-10 11:49:59 -07:00 |
|
lut_intermediate_buffer_example.svg
|
[Doc] Add svg figures for LUT examples
|
2020-11-26 12:35:39 -07:00 |
|
meas_edge.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
memory_bank.png
|
[Doc] update documentation about memory bank definition
|
2020-10-29 17:04:25 -06:00 |
|
memory_bank_decoder.svg
|
[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank
|
2021-10-04 12:09:42 -07:00 |
|
memory_bank_flatten.svg
|
[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank
|
2021-10-04 12:09:42 -07:00 |
|
memory_bank_shift_register.svg
|
[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank
|
2021-10-04 12:09:42 -07:00 |
|
multi_mode_dpram128x8_memory_circuit_model.svg
|
[Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples
|
2021-05-24 14:50:55 -06:00 |
|
multi_mode_ff_circuit_model.svg
|
[Doc] Add example circuit model about multi-mode flip-flops; Separate data-path FF circuit model and configuration-chain FF circuit model;
|
2021-05-24 13:03:40 -06:00 |
|
multi_mode_mult8x8_circuit_model.svg
|
[Doc] Add example circuit models for multipliers and update technical highlight with links to the examples
|
2021-05-24 15:24:50 -06:00 |
|
multi_region_config_chains.png
|
[Documentation] Update documentation about the multi-region configuration
|
2020-09-29 15:55:42 -06:00 |
|
mux.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
mux1lvl.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
native_frac_lut.svg
|
[Doc] Bug fix in LUT circuit model documentation
|
2020-12-04 14:44:27 -07:00 |
|
pass-gate.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
pass_transistor.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
point2point_example.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
point2point_truthtable.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
shrink_boundary.png
|
[doc] add description about new option ``shrink_boundary``
|
2023-08-12 12:25:38 -07:00 |
|
single_lut3_example.svg
|
[Doc] Patch the schematic of LUT circuit models to be consistent with netlists
|
2021-03-15 11:40:09 -06:00 |
|
single_mode_dpram128x8_memory_circuit_model.svg
|
[Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples
|
2021-05-24 14:50:55 -06:00 |
|
single_mode_mult8x8_circuit_model.svg
|
[Doc] Add example circuit models for multipliers and update technical highlight with links to the examples
|
2021-05-24 15:24:50 -06:00 |
|
sram_blwl.png
|
update documentation about the frame-based configuration protocol
|
2020-06-11 19:31:11 -06:00 |
|
sram_blwlr.svg
|
[Doc] Add missing figures
|
2021-09-20 20:31:53 -07:00 |
|
std_frac_lut.svg
|
[Doc] Bug fix in LUT circuit model documentation
|
2020-12-04 14:44:27 -07:00 |
|
thru_channel.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
vanilla_config_protocol.png
|
update documentation for standalone configuration protocol
|
2020-06-11 19:31:13 -06:00 |
|
wire.png
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
d9e3392194
