147 lines
5.5 KiB
C++
147 lines
5.5 KiB
C++
#ifndef CONFIG_PROTOCOL_H
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#define CONFIG_PROTOCOL_H
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#include <map>
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#include <string>
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#include "circuit_library_fwd.h"
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#include "circuit_types.h"
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#include "openfpga_port.h"
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#include "ql_memory_bank_config_setting.h"
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/* Data type to define the protocol through which BL/WL can be manipulated */
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enum e_blwl_protocol_type {
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BLWL_PROTOCOL_FLATTEN,
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BLWL_PROTOCOL_DECODER,
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BLWL_PROTOCOL_SHIFT_REGISTER,
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NUM_BLWL_PROTOCOL_TYPES
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};
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constexpr std::array<const char*, NUM_BLWL_PROTOCOL_TYPES>
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BLWL_PROTOCOL_TYPE_STRING = {{"flatten", "decoder", "shift_register"}};
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/********************************************************************
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* A data structure to store configuration protocol information
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*******************************************************************/
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class ConfigProtocol {
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public: /* Constructors */
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ConfigProtocol();
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public: /* Public Accessors */
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e_config_protocol_type type() const;
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std::string memory_model_name() const;
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CircuitModelId memory_model() const;
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int num_regions() const;
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/* Find the number of programming clocks, only valid for configuration chain
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* type! */
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size_t num_prog_clocks() const;
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/* Get information of the programming clock port: name and width */
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openfpga::BasicPort prog_clock_port_info() const;
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/* Get a list of programming clock pins, flatten from the programming clock
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* port */
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std::vector<openfpga::BasicPort> prog_clock_pins() const;
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/* Get a list of programming clock ports */
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std::string prog_clock_pin_ccff_head_indices_str(
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const openfpga::BasicPort& port) const;
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std::vector<size_t> prog_clock_pin_ccff_head_indices(
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const openfpga::BasicPort& port) const;
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e_blwl_protocol_type bl_protocol_type() const;
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std::string bl_memory_model_name() const;
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CircuitModelId bl_memory_model() const;
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size_t bl_num_banks() const;
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e_blwl_protocol_type wl_protocol_type() const;
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std::string wl_memory_model_name() const;
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CircuitModelId wl_memory_model() const;
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size_t wl_num_banks() const;
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/* QL Memory Bank Config Setting */
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const QLMemoryBankConfigSetting* ql_memory_bank_config_setting() const;
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public: /* Public Mutators */
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void set_type(const e_config_protocol_type& type);
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void set_memory_model_name(const std::string& memory_model_name);
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void set_memory_model(const CircuitModelId& memory_model);
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void set_num_regions(const int& num_regions);
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/* Add the programming clock port */
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void set_prog_clock_port(const openfpga::BasicPort& port);
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/* Add a pair of programming clock pin and ccff head indices. This API will
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* parse the index list, e.g., "0,1" to a vector of integers [0 1] */
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void set_prog_clock_pin_ccff_head_indices_pair(
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const openfpga::BasicPort& pin, const std::string& indices_str);
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void set_bl_protocol_type(const e_blwl_protocol_type& type);
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void set_bl_memory_model_name(const std::string& memory_model_name);
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void set_bl_memory_model(const CircuitModelId& memory_model);
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void set_bl_num_banks(const size_t& num_banks);
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void set_wl_protocol_type(const e_blwl_protocol_type& type);
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void set_wl_memory_model_name(const std::string& memory_model_name);
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void set_wl_memory_model(const CircuitModelId& memory_model);
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void set_wl_num_banks(const size_t& num_banks);
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/* QL Memory Bank Config Setting */
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QLMemoryBankConfigSetting* get_ql_memory_bank_config_setting();
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public: /* Public validators */
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/* Check if internal data has any conflicts to each other. Return number of
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* errors detected */
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int validate() const;
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private: /* Private validators */
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/* For configuration chains, to validate if
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* - programming clocks is smaller than the number of regions
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* - programming clocks does not have any conflicts in controlling regions (no
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* overlaps)
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* - each region has been assigned to a programming clock
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* Return number of errors detected
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*/
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int validate_ccff_prog_clocks() const;
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private: /* Internal data */
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/* The type of configuration protocol.
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* In other words, it is about how to organize and access each configurable
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* memory
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*/
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e_config_protocol_type type_;
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/* The circuit model of configuration memory to be used in the protocol */
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std::string memory_model_name_;
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CircuitModelId memory_model_;
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/* Number of configurable regions */
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int num_regions_;
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/* Programming clock managment: This is only applicable to configuration chain
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* protocols */
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openfpga::BasicPort prog_clk_port_;
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std::vector<std::vector<size_t>> prog_clk_ccff_head_indices_;
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char INDICE_STRING_DELIM_;
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/* BL & WL protocol: This is only applicable to memory-bank configuration
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* protocols
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* - type: defines which protocol to be used. By default, we
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* consider decoders
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* - bl/wl_memory_model: defines the circuit model to be used when building
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* shift register chains for BL/WL configuration. It must be a valid CCFF
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* circuit model. This is only applicable when shift-register protocol is
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* selected for BL or WL.
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* - bl/wl_num_banks: defines the number of independent shift register
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* chains (with separated head and tail ports) for a given BL protocol per
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* configuration region
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*/
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e_blwl_protocol_type bl_protocol_type_ = BLWL_PROTOCOL_DECODER;
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std::string bl_memory_model_name_;
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CircuitModelId bl_memory_model_;
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size_t bl_num_banks_;
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e_blwl_protocol_type wl_protocol_type_ = BLWL_PROTOCOL_DECODER;
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std::string wl_memory_model_name_;
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CircuitModelId wl_memory_model_;
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size_t wl_num_banks_;
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/* QL Memory Bank Config Setting */
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QLMemoryBankConfigSetting ql_memory_bank_config_setting_;
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};
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#endif
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