80 lines
2.8 KiB
C++
80 lines
2.8 KiB
C++
/********************************************************************
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* This file includes functions to generate Verilog submodules for LUTs
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********************************************************************/
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#include <string>
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#include <algorithm>
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#include "util.h"
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#include "vtr_assert.h"
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/* Device-level header files */
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#include "mux_graph.h"
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#include "module_manager.h"
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#include "physical_types.h"
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#include "vpr_types.h"
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#include "mux_utils.h"
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/* FPGA-X2P context header files */
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#include "spice_types.h"
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#include "fpga_x2p_naming.h"
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#include "fpga_x2p_utils.h"
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/* FPGA-Verilog context header files */
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#include "verilog_writer_utils.h"
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#include "verilog_module_writer.h"
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#include "verilog_lut.h"
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/********************************************************************
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* Print Verilog modules for the Look-Up Tables (LUTs)
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* in the circuit library
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********************************************************************/
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void print_verilog_submodule_luts(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const std::string& verilog_dir,
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const std::string& submodule_dir,
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const bool& use_explicit_port_map) {
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/* TODO: remove .bak when this part is completed and tested */
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std::string verilog_fname = submodule_dir + luts_verilog_file_name + ".bak";
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std::fstream fp;
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/* Create the file stream */
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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/* Check if the file stream if valid or not */
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check_file_handler(fp);
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/* Create file */
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vpr_printf(TIO_MESSAGE_INFO,
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"Generating Verilog netlist for LUTs (%s)...\n",
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verilog_fname.c_str());
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print_verilog_file_header(fp, "Look-Up Tables");
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print_verilog_include_defines_preproc_file(fp, verilog_dir);
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/* Search for each LUT circuit model */
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for (const auto& lut_model : circuit_lib.models()) {
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/* Bypass user-defined and non-LUT modules */
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if ( (!circuit_lib.model_verilog_netlist(lut_model).empty())
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|| (SPICE_MODEL_LUT != circuit_lib.model_type(lut_model)) ) {
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continue;
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}
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/* Find the module id */
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ModuleId lut_module = module_manager.find_module(circuit_lib.model_name(lut_model));
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VTR_ASSERT(true == module_manager.valid_module_id(lut_module));
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write_verilog_module_to_file(fp, module_manager, lut_module,
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use_explicit_port_map || circuit_lib.dump_explicit_port_map(lut_model));
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}
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/* Close the file handler */
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fp.close();
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/* Add fname to the linked list */
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/* Add it when the Verilog generation is refactored
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submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
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*/
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return;
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}
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