tangxifan 0db4ef62e8 [test] add a new test for tile-based fabric: using preconfig testbenches		2023-07-25 15:48:14 -07:00
..
bottom_right_custom_pins/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
homo_fabric_tile/config	[test] add a new test for top-left tile grouping	2023-07-19 11:22:36 -07:00
homo_fabric_tile_preconfig/config	[test] add a new test for tile-based fabric: using preconfig testbenches	2023-07-25 15:48:14 -07:00
io_subtile/config	[test] now testcases are using proper arch	2023-05-03 21:47:21 +08:00
tileable_io/config	[test] now testcases are using proper arch	2023-05-03 21:47:21 +08:00
top_left_custom_pins/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
top_right_custom_pins/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00