tangxifan 82ed6b177b [FPGA-Verilog] Now consider clock constraints for BL/WL shift registers		2021-10-06 11:39:28 -07:00
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src	[FPGA-Verilog] Now consider clock constraints for BL/WL shift registers	2021-10-06 11:39:28 -07:00
CMakeLists.txt	[Tool] Deploy pin constraints to preconfig Verilog module generation	2021-01-19 16:56:30 -07:00