Lalit Sharma a073572884 Fixing regression errors by removing opt_rmdff from yosys ys as now this is included by default ... Resolving conflicts during rebase to master		2021-04-14 05:50:02 -07:00
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arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	Merge branch 'master' into hetergeneous_arch	2021-03-23 17:05:03 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Fixing regression errors by removing opt_rmdff from yosys ys as now this is included by default	2021-04-14 05:50:02 -07:00
openfpga_arch	Merge branch 'master' into hetergeneous_arch	2021-03-23 17:05:03 -06:00
openfpga_cell_library	[HDL] Add HDL for 8-bit single-mode multiplier	2021-03-23 15:36:09 -06:00
openfpga_shell_scripts	Merge branch 'master' into fpga_sdc_test	2021-04-11 21:14:46 -06:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
openfpga_yosys_techlib	Merge branch 'master' into hetergeneous_arch	2021-03-23 17:05:03 -06:00
regression_test_scripts	[Test] Update regression test with new SDC tests	2021-04-11 20:24:32 -06:00
scripts	[Script] Add tolerance options to check qor script	2021-03-23 12:26:33 -06:00
tasks	Merge branch 'master' into fpga_sdc_test	2021-04-11 21:14:46 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	Merge branch 'master' into hetergeneous_arch	2021-03-23 17:05:03 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00