tangxifan 025ee67bc7 [Engine] Clear up compiler warning in tileable rr_graph builder		2021-09-24 15:20:43 -07:00
..
analysis	add vpr8 libs and core engine for further integration	2020-01-03 16:14:42 -07:00
base	reduce activity error to warning.	2020-04-22 17:36:02 -06:00
device	Disabled printing segment ids for non-channel nodes.	2020-11-23 17:07:28 +01:00
draw	correct missing rr_nodes usage to rr_graph obj	2020-02-04 16:48:15 -07:00
pack	[Tool] Borrow a quick fix from the VPR pull request https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1656/files	2021-02-04 17:30:49 -07:00
place	bug fixing for heterogenenous FPGA when using the RRGraph object	2020-02-04 17:31:39 -07:00
power	power estimation adapted to use RRGraph object	2020-02-01 12:26:42 -07:00
route	Added loading rr node segment indices	2020-11-23 14:53:50 +01:00
tileable_rr_graph	[Engine] Clear up compiler warning in tileable rr_graph builder	2021-09-24 15:20:43 -07:00
timing	net delay adopt RRGraph object, compile with no errors	2020-02-01 22:38:21 -07:00
util	correct missing rr_nodes usage to rr_graph obj	2020-02-04 16:48:15 -07:00
main.cpp	add vpr8 libs and core engine for further integration	2020-01-03 16:14:42 -07:00