128 lines
4.5 KiB
C++
128 lines
4.5 KiB
C++
/********************************************************************
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* This file includes functions that outputs an OpenFPGAArch
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* data structure to XML format
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*******************************************************************/
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#include <fstream>
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/* Headers from vtrutil library */
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#include "vtr_time.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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/* Headers from readarchopenfpga library */
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#include "write_xml_bitstream_setting.h"
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#include "write_xml_circuit_library.h"
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#include "write_xml_config_protocol.h"
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#include "write_xml_openfpga_arch.h"
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#include "write_xml_pb_type_annotation.h"
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#include "write_xml_routing_circuit.h"
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#include "write_xml_simulation_setting.h"
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#include "write_xml_technology_library.h"
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#include "write_xml_tile_annotation.h"
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/********************************************************************
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* A writer to output an OpenFPGA arch database to XML format
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*******************************************************************/
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void write_xml_openfpga_arch(const char* fname,
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const openfpga::Arch& openfpga_arch) {
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vtr::ScopedStartFinishTimer timer("Write OpenFPGA architecture");
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/* Create a file handler */
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std::fstream fp;
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/* Open the file stream */
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fp.open(std::string(fname), std::fstream::out | std::fstream::trunc);
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/* Validate the file stream */
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openfpga::check_file_stream(fname, fp);
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/* Write the root node for openfpga_arch */
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fp << "<openfpga_architecture>"
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<< "\n";
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/* Write the technology library */
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write_xml_technology_library(fp, fname, openfpga_arch.tech_lib);
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/* Write the circuit library */
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write_xml_circuit_library(fp, fname, openfpga_arch.circuit_lib);
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/* Write the configuration protocol */
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write_xml_config_protocol(fp, fname, openfpga_arch.config_protocol,
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openfpga_arch.circuit_lib);
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/* Write the connection block circuit definition */
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write_xml_cb_switch_circuit(fp, fname, openfpga_arch.circuit_lib,
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openfpga_arch.cb_switch2circuit);
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/* Write the switch block circuit definition */
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write_xml_sb_switch_circuit(fp, fname, openfpga_arch.circuit_lib,
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openfpga_arch.sb_switch2circuit);
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/* Write the routing segment circuit definition */
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write_xml_routing_segment_circuit(fp, fname, openfpga_arch.circuit_lib,
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openfpga_arch.routing_seg2circuit);
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/* Write the direct connection circuit definition */
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write_xml_direct_circuit(fp, fname, openfpga_arch.circuit_lib,
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openfpga_arch.arch_direct);
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/* Write the pb_type annotations */
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openfpga::write_xml_tile_annotations(fp, fname,
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openfpga_arch.tile_annotations);
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/* Write the pb_type annotations */
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openfpga::write_xml_pb_type_annotations(fp, fname,
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openfpga_arch.pb_type_annotations);
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fp << "</openfpga_architecture>"
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<< "\n";
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/* Close the file stream */
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fp.close();
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}
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/********************************************************************
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* A writer to output an OpenFPGA simulation setting database to XML format
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*******************************************************************/
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void write_xml_openfpga_simulation_settings(
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const char* fname, const openfpga::SimulationSetting& openfpga_sim_setting) {
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vtr::ScopedStartFinishTimer timer("Write OpenFPGA simulation settings");
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/* Create a file handler */
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std::fstream fp;
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/* Open the file stream */
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fp.open(std::string(fname), std::fstream::out | std::fstream::trunc);
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/* Validate the file stream */
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openfpga::check_file_stream(fname, fp);
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/* Write the simulation */
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write_xml_simulation_setting(fp, fname, openfpga_sim_setting);
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/* Close the file stream */
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fp.close();
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}
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/********************************************************************
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* A writer to output an OpenFPGA bitstream setting database to XML format
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*******************************************************************/
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void write_xml_openfpga_bitstream_settings(
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const char* fname,
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const openfpga::BitstreamSetting& openfpga_bitstream_setting) {
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vtr::ScopedStartFinishTimer timer("Write OpenFPGA bitstream settings");
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/* Create a file handler */
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std::fstream fp;
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/* Open the file stream */
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fp.open(std::string(fname), std::fstream::out | std::fstream::trunc);
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/* Validate the file stream */
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openfpga::check_file_stream(fname, fp);
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/* Write the simulation */
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write_xml_bitstream_setting(fp, fname, openfpga_bitstream_setting);
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/* Close the file stream */
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fp.close();
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}
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