52 lines
732 B
Verilog
52 lines
732 B
Verilog
module dpram (
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input clk,
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input wen,
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input ren,
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input[9:0] waddr,
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input[9:0] raddr,
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input[31:0] d_in,
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output[31:0] d_out );
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dual_port_sram memory_0 (
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.wclk (clk),
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.wen (wen),
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.waddr (waddr),
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.data_in (d_in),
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.rclk (clk),
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.ren (ren),
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.raddr (raddr),
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.d_out (d_out) );
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endmodule
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module dual_port_sram (
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input wclk,
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input wen,
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input[9:0] waddr,
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input[31:0] data_in,
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input rclk,
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input ren,
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input[9:0] raddr,
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output[31:0] d_out );
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reg[31:0] ram[1023:0];
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reg[31:0] internal;
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assign d_out = internal;
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always @(posedge wclk) begin
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if(wen) begin
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ram[waddr] <= data_in;
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end
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end
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always @(posedge rclk) begin
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if(ren) begin
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internal <= ram[raddr];
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end
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end
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endmodule
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