40 lines
1.9 KiB
ReStructuredText
40 lines
1.9 KiB
ReStructuredText
Command-line Options for FPGA-Verilog Generator
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All the command line options of FPGA-Verilog can be shown by calling the help menu of VPR. Here are all the FPGA-Verilog-related options that you can find:
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FPGA-Verilog Supported Options::
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--fpga_verilog
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--fpga_verilog_dir <directory_path_of_dumped_verilog_files>
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--fpga_verilog_include_timing
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--fpga_verilog_init_sim
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--fpga_verilog_print_modelsim_autodeck
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--fpga_verilog_modelsim_ini_path <string>
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--fpga_verilog_print_top_testbench
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--fpga_verilog_print_top_auto_testbench <path_to_the_verilog_benchmark>
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.. csv-table:: Commmand-line Options of FPGA-Verilog
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:header: "Command Options", "Description"
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:widths: 15, 30
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"--fpga_verilog", "Turn on the FPGA-Verilog."
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"--fpga_verilog_dir <dir_path>", "Specify the directory that all the Verilog files will be outputted to. <dir_path> is the destination directory."
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"--fpga_verilog_include_timing", "Includes the timings found in the XML file."
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"--fpga_verilog_init_sim", "Initializes the simulation for ModelSim."
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"--fpga_verilog_print_modelsim_autodeck", "Generates the scripts necessary to the ModelSim simulation."
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"--fpga_verilog_modelsim_ini_path <string>", "Gives the path for the .ini necessary to ModelSim."
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"--fpga_verilog_print_top_testbench", "Print the full-chip-level testbench for the FPGA. Determines the type of autodeck."
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"--fpga_verilog_print_top_auto_testbench \
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<path_to_the_verilog_benchmark>", "Prints the testbench associated with the given benchmark. Determines the type of autodeck."
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.. note:: The selected directory will contain the *Verilog top file* and three other folders. The folders are:
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* **sub_module:** contains each module verilog file and is more detailed in the next part *Verilog Output File Format*.
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* **routing:** contains the Verilog for the connection blocks and the switch boxes.
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* **lb:** contains the grids Verilog files.
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