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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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7b611601fc
OpenFPGA
/
openfpga_flow
/
tasks
/
quicklogic_tests
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coolbreeze413
840fa399c6
enable single counter test (fails, needs debug)
2021-11-09 21:36:33 +05:30
..
counter_5clock_test
/config
update tests to use no_ff_map and remove tests that need async set/reset for now
2021-03-10 10:04:45 -08:00
flow_test
/config
enable single counter test (fails, needs debug)
2021-11-09 21:36:33 +05:30
lut_adder_test
/config
[Test] Deploy the newly added adder benchmarks to tests
2021-06-30 15:14:24 -06:00
sdc_controller_test
/config
Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
2021-02-25 23:39:07 -08:00