tangxifan 27b619554d add stats for verilog modules		2019-08-23 20:23:42 -06:00
..
base	try to fix the bug in clock net identification	2019-08-13 16:47:28 -06:00
device	minor fix for OSX and update travis using ccache to speed up compilation	2019-08-21 15:25:36 -06:00
fpga_x2p	add stats for verilog modules	2019-08-23 20:23:42 -06:00
mrfpga	cleaned unused variables	2019-05-13 14:45:02 -06:00
pack	cleaned unused variables	2019-05-13 14:45:02 -06:00
place	add option to compact tileable routing arch	2019-07-04 17:13:34 -06:00
power	bug fixing for memory leaking in allocating pb_rr_graph and power estimation	2019-06-15 12:23:36 -06:00
route	keep route file updated with tileable rr_graph	2019-08-13 15:37:42 -06:00
timing	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
util	basically finished the coding of tileable rr_graph generator. testing to go	2019-06-20 18:17:07 -06:00
ctags_vpr_src.sh	memory sanitized	2019-08-13 14:19:40 -06:00
main.c	cleaned unused variables	2019-05-13 14:45:02 -06:00
shell_main.c	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00