Maciej Kurc 782cdfd8e1 Added VPR commandline options that control unconnected port handling in the output Verilog netlist ... Signed-off-by: Maciej Kurc <mkurc@antmicro.com>		2022-06-30 13:06:34 +02:00
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scripts	add vpr8 libs and core engine for further integration	2020-01-03 16:14:42 -07:00
src	Added VPR commandline options that control unconnected port handling in the output Verilog netlist	2022-06-30 13:06:34 +02:00
test	add vpr8 libs and core engine for further integration	2020-01-03 16:14:42 -07:00
CMakeLists.txt	remove obselete codes and update regression tests	2020-07-04 17:31:34 -06:00
main.ui	add vpr8 libs and core engine for further integration	2020-01-03 16:14:42 -07:00
valgrind.supp	bring RRGraph object and writer online	2020-01-31 16:39:40 -07:00