tangxifan 3369d724e9 bug fixing in Verilog top-level testbench generation		2020-04-05 17:50:11 -06:00
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src	bug fixing in Verilog top-level testbench generation	2020-04-05 17:50:11 -06:00
test_blif	add missing files for micro benchmarks	2020-03-20 11:08:55 -06:00
test_openfpga_arch	bug fixed in gpio naming for module manager ports	2020-04-05 17:26:44 -06:00
test_script	add testing script for the spy io	2020-04-05 15:24:40 -06:00
test_vpr_arch	added FPGA architecture with I/Os on the left and right sides	2020-04-01 15:46:38 -06:00
CMakeLists.txt	add simulation ini file writer	2020-02-27 18:01:47 -07:00