riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/openfpga
History
tangxifan 21d1519658 [Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option 2021-06-24 16:56:28 -06:00
..
src [Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option 2021-06-24 16:56:28 -06:00
CMakeLists.txt [Tool] Deploy pin constraints to preconfig Verilog module generation 2021-01-19 16:56:30 -07:00