tangxifan 77529f4957 adapt top Verilog testbench generation		2020-02-26 21:30:21 -07:00
..
src	adapt top Verilog testbench generation	2020-02-26 21:30:21 -07:00
test_blif	use a micro benchmark for vpr quick-run	2020-01-26 17:56:22 -07:00
test_openfpga_arch	bug fixing for lb router. Add physical mode to default node expanding settings	2020-02-21 11:29:00 -07:00
test_script	add io location map data structure and start porting verilog testbench generator	2020-02-26 17:10:57 -07:00
test_vpr_arch	bug fixing for lb router. Add physical mode to default node expanding settings	2020-02-21 11:29:00 -07:00
CMakeLists.txt	start implement openfpga shell and use vpr as a macro	2020-01-22 20:20:10 -07:00