tangxifan 76d58ebaa0 [FPGA-Verilog] Move clock generator to generic stimuli and shift register clock period is auto tuned by programming clock period		2021-10-02 21:48:10 -07:00
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src	[FPGA-Verilog] Move clock generator to generic stimuli and shift register clock period is auto tuned by programming clock period	2021-10-02 21:48:10 -07:00
CMakeLists.txt	[Tool] Deploy pin constraints to preconfig Verilog module generation	2021-01-19 16:56:30 -07:00