45 lines
686 B
Verilog
45 lines
686 B
Verilog
module $__MY_DPRAM (
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output[31:0] B1DATA,
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input CLK1,
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input[9:0] B1ADDR,
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input[9:0] A1ADDR,
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input[31:0] A1DATA,
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input A1EN,
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input B1EN );
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generate
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dpram #() _TECHMAP_REPLACE_ (
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.clk (CLK1),
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.wen (A1EN),
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.waddr (A1ADDR),
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.d_in (A1DATA),
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.ren (B1EN),
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.raddr (B1ADDR),
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.d_out (B1DATA) );
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endgenerate
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endmodule
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module $__MY_SPRAM (
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output[31:0] B1DATA,
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input CLK1,
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input[9:0] B1ADDR,
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input[9:0] A1ADDR,
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input[31:0] A1DATA,
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input A1EN );
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generate
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dpram #() _TECHMAP_REPLACE_ (
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.clk (CLK1),
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.wen (A1EN),
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.waddr (A1ADDR),
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.d_in (A1DATA),
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.ren (1'b1),
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.raddr (A1ADDR),
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.d_out (B1DATA) );
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endgenerate
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endmodule
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