328 lines
18 KiB
C++
328 lines
18 KiB
C++
/********************************************************************
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* Add commands to the OpenFPGA shell interface,
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* in purpose of generate Verilog netlists modeling the full FPGA fabric
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* This is one of the core engine of openfpga, including:
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* - generate_fabric_verilog : generate Verilog netlists about FPGA fabric
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* - generate_fabric_verilog_testbench : TODO: generate Verilog testbenches
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*******************************************************************/
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#include "openfpga_verilog.h"
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#include "openfpga_verilog_command.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* - Add a command to Shell environment: generate fabric Verilog
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* - Add associated options
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* - Add command dependency
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*******************************************************************/
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static
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ShellCommandId add_openfpga_write_fabric_verilog_command(openfpga::Shell<OpenfpgaContext>& shell,
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const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds) {
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Command shell_cmd("write_fabric_verilog");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the output directory for Verilog netlists");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* Add an option '--explicit_port_mapping' */
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shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
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/* Add an option '--include_timing' */
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shell_cmd.add_option("include_timing", false, "Enable timing annotation in Verilog netlists");
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/* Add an option '--print_user_defined_template' */
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shell_cmd.add_option("print_user_defined_template", false, "Generate a template Verilog files for user-defined circuit models");
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/* Add an option '--default_net_type' */
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CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
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shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
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/* Add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "Enable verbose output");
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/* Add command 'write_fabric_verilog' to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate Verilog netlists modeling full FPGA fabric");
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(shell_cmd_id, write_fabric_verilog);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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/********************************************************************
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* - add a command to shell environment: write full testbench
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* - add associated options
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* - add command dependency
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*******************************************************************/
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static
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ShellCommandId add_openfpga_write_full_testbench_command(openfpga::Shell<OpenfpgaContext>& shell,
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const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds) {
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Command shell_cmd("write_full_testbench");
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/* add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option("file", true, "specify the output directory for hdl netlists");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* add an option '--bitstream'*/
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CommandOptionId bitstream_opt = shell_cmd.add_option("bitstream", true, "specify the bitstream to be loaded in the testbench");
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shell_cmd.set_option_require_value(bitstream_opt, openfpga::OPT_STRING);
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/* add an option '--fabric_netlist_file_path'*/
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CommandOptionId fabric_netlist_opt = shell_cmd.add_option("fabric_netlist_file_path", false, "specify the file path to the fabric hdl netlist");
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shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING);
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/* add an option '--pin_constraints_file in short '-pcf' */
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CommandOptionId pcf_opt = shell_cmd.add_option("pin_constraints_file", false, "specify the file path to the pin constraints");
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shell_cmd.set_option_short_name(pcf_opt, "pcf");
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shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING);
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/* add an option '--reference_benchmark_file_path'*/
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CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", false, "specify the file path to the reference verilog netlist. If specified, the testbench will include self-checking codes");
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shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
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/* add an option '--fast_configuration' */
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shell_cmd.add_option("fast_configuration", false, "reduce the period of configuration by skip certain data points");
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/* add an option '--explicit_port_mapping' */
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shell_cmd.add_option("explicit_port_mapping", false, "use explicit port mapping in verilog netlists");
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/* Add an option '--default_net_type' */
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CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
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shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
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/* Add an option '--no_self_checking' */
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shell_cmd.add_option("no_self_checking", false, "Do not generate self-checking codes for Verilog testbenches.");
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/* add an option '--include_signal_init' */
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shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
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/* add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "enable verbose output");
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/* add command to the shell */
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ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate full testbenches for an fpga fabric");
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(shell_cmd_id, write_full_testbench);
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/* add command dependency to the shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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/********************************************************************
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* - add a command to shell environment: write preconfigured fabric wrapper
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* - add associated options
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* - add command dependency
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*******************************************************************/
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static
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ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command(openfpga::Shell<OpenfpgaContext>& shell,
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const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds) {
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Command shell_cmd("write_preconfigured_fabric_wrapper");
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/* add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option("file", true, "specify the output directory for hdl netlists");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* add an option '--fabric_netlist_file_path'*/
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CommandOptionId fabric_netlist_opt = shell_cmd.add_option("fabric_netlist_file_path", false, "specify the file path to the fabric hdl netlist");
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shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING);
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/* add an option '--pin_constraints_file in short '-pcf' */
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CommandOptionId pcf_opt = shell_cmd.add_option("pin_constraints_file", false, "specify the file path to the pin constraints");
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shell_cmd.set_option_short_name(pcf_opt, "pcf");
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shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING);
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/* add an option '--explicit_port_mapping' */
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shell_cmd.add_option("explicit_port_mapping", false, "use explicit port mapping in verilog netlists");
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/* Add an option '--default_net_type' */
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CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
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shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
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/* Add an option '--embed_bitstream' */
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CommandOptionId embed_bitstream_opt = shell_cmd.add_option("embed_bitstream", false, "Embed bitstream to the Verilog wrapper netlist; This may cause a large netlist file size");
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shell_cmd.set_option_require_value(embed_bitstream_opt, openfpga::OPT_STRING);
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/* add an option '--include_signal_init' */
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shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
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/* add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "enable verbose output");
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/* add command to the shell */
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ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate a wrapper for a pre-configured fpga fabric");
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(shell_cmd_id, write_preconfigured_fabric_wrapper);
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/* add command dependency to the shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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/********************************************************************
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* - Add a command to Shell environment: write preconfigured testbench
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* - Add associated options
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* - Add command dependency
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*******************************************************************/
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static
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ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shell<OpenfpgaContext>& shell,
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const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds) {
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Command shell_cmd("write_preconfigured_testbench");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the output directory for HDL netlists");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* add an option '--fabric_netlist_file_path'*/
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CommandOptionId fabric_netlist_opt = shell_cmd.add_option("fabric_netlist_file_path", false, "specify the file path to the fabric hdl netlist");
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shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING);
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/* Add an option '--pin_constraints_file in short '-pcf' */
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CommandOptionId pcf_opt = shell_cmd.add_option("pin_constraints_file", false, "Specify the file path to the pin constraints");
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shell_cmd.set_option_short_name(pcf_opt, "pcf");
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shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING);
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/* Add an option '--reference_benchmark_file_path'*/
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CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", false, "Specify the file path to the reference Verilog netlist. If specified, the testbench will include self-checking codes");
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shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
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/* Add an option '--explicit_port_mapping' */
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shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
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/* Add an option '--default_net_type' */
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CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
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shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
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/* Add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "Enable verbose output");
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/* Add command to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate testbenches for a preconfigured FPGA fabric");
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(shell_cmd_id, write_preconfigured_testbench);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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/********************************************************************
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* - Add a command to Shell environment: write simulation task info
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* - Add associated options
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* - Add command dependency
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*******************************************************************/
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static
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ShellCommandId add_openfpga_write_simulation_task_info_command(openfpga::Shell<OpenfpgaContext>& shell,
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const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds) {
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Command shell_cmd("write_simulation_task_info");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the file path to output simulation-related information");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* Add an option '--hdl_dir'*/
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CommandOptionId hdl_dir_opt = shell_cmd.add_option("hdl_dir", true, "Specify the directory path where HDL netlists are created");
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shell_cmd.set_option_require_value(hdl_dir_opt, openfpga::OPT_STRING);
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/* Add an option '--reference_benchmark_file_path'*/
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CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", false, "Specify the file path to the reference Verilog netlist. If specified, the testbench will include self-checking codes");
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shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
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/* Add an option '--testbench_type'*/
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CommandOptionId tb_type_opt = shell_cmd.add_option("testbench_type", false, "Specify the type of testbenches to be considered. Different testbenches have different simulation parameters.");
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shell_cmd.set_option_require_value(tb_type_opt, openfpga::OPT_STRING);
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/* Add an option '--time_unit' */
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CommandOptionId time_unit_opt = shell_cmd.add_option("time_unit", false, "Specify the time unit to be used in HDL simulation. Acceptable is [a|f|p|n|u|m|k|M]s");
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shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING);
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/* Add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "Enable verbose output");
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/* Add command to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate an interchangable simulation task configuration file");
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(shell_cmd_id, write_simulation_task_info);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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void add_openfpga_verilog_commands(openfpga::Shell<OpenfpgaContext>& shell) {
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/* Get the unique id of 'build_fabric' command which is to be used in creating the dependency graph */
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const ShellCommandId& build_fabric_cmd_id = shell.command(std::string("build_fabric"));
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/* Add a new class of commands */
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ShellCommandClassId openfpga_verilog_cmd_class = shell.add_command_class("FPGA-Verilog");
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/********************************
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* Command 'write_fabric_verilog'
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*/
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/* The 'write_fabric_verilog' command should NOT be executed before 'build_fabric' */
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std::vector<ShellCommandId> fabric_verilog_dependent_cmds;
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fabric_verilog_dependent_cmds.push_back(build_fabric_cmd_id);
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add_openfpga_write_fabric_verilog_command(shell,
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openfpga_verilog_cmd_class,
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fabric_verilog_dependent_cmds);
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/********************************
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* Command 'write_full_testbench'
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*/
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/* The command 'write_full_testbench' should NOT be executed before 'build_fabric' */
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std::vector<ShellCommandId> full_testbench_dependent_cmds;
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full_testbench_dependent_cmds.push_back(build_fabric_cmd_id);
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add_openfpga_write_full_testbench_command(shell,
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openfpga_verilog_cmd_class,
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full_testbench_dependent_cmds);
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/********************************
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* Command 'write_preconfigured_fabric_wrapper'
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*/
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/* The command 'write_preconfigured_fabric_wrapper' should NOT be executed before 'build_fabric' */
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std::vector<ShellCommandId> preconfig_wrapper_dependent_cmds;
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preconfig_wrapper_dependent_cmds.push_back(build_fabric_cmd_id);
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add_openfpga_write_preconfigured_fabric_wrapper_command(shell,
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openfpga_verilog_cmd_class,
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preconfig_wrapper_dependent_cmds);
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/********************************
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* Command 'write_preconfigured_testbench'
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*/
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/* The command 'write_preconfigured_testbench' should NOT be executed before 'build_fabric' */
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std::vector<ShellCommandId> preconfig_testbench_dependent_cmds;
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preconfig_testbench_dependent_cmds.push_back(build_fabric_cmd_id);
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add_openfpga_write_preconfigured_testbench_command(shell,
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openfpga_verilog_cmd_class,
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preconfig_testbench_dependent_cmds);
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/********************************
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* Command 'write_simulation_task_info'
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*/
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/* The command 'write_simulation_task_info' should NOT be executed before 'build_fabric' */
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std::vector<ShellCommandId> sim_task_info_dependent_cmds;
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sim_task_info_dependent_cmds.push_back(build_fabric_cmd_id);
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add_openfpga_write_simulation_task_info_command(shell,
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openfpga_verilog_cmd_class,
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sim_task_info_dependent_cmds);
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}
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} /* end namespace openfpga */
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