277 lines
15 KiB
C++
277 lines
15 KiB
C++
/********************************************************************
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* This file includes functions to compress the hierachy of routing architecture
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*******************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_time.h"
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#include "vtr_log.h"
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/* Headers from openfpgashell library */
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#include "command_exit_codes.h"
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/* Headers from openfpgautil library */
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#include "openfpga_scale.h"
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#include "verilog_api.h"
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#include "openfpga_verilog.h"
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/* Headers from pcf library */
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#include "read_xml_pin_constraints.h"
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/* Include global variables of VPR */
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#include "globals.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* A wrapper function to call the fabric Verilog generator of FPGA-Verilog
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*******************************************************************/
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int write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context) {
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CommandOptionId opt_output_dir = cmd.option("file");
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CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
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CommandOptionId opt_include_timing = cmd.option("include_timing");
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CommandOptionId opt_print_user_defined_template = cmd.option("print_user_defined_template");
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CommandOptionId opt_default_net_type = cmd.option("default_net_type");
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CommandOptionId opt_verbose = cmd.option("verbose");
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/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
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* Keep it independent from any other outside data structures
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*/
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FabricVerilogOption options;
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options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
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options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
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options.set_include_timing(cmd_context.option_enable(cmd, opt_include_timing));
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options.set_print_user_defined_template(cmd_context.option_enable(cmd, opt_print_user_defined_template));
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if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
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options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));
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}
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options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
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options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing());
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fpga_fabric_verilog(openfpga_ctx.mutable_module_graph(),
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openfpga_ctx.mutable_verilog_netlists(),
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openfpga_ctx.arch().circuit_lib,
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openfpga_ctx.mux_lib(),
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openfpga_ctx.decoder_lib(),
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g_vpr_ctx.device(),
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openfpga_ctx.vpr_device_annotation(),
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openfpga_ctx.device_rr_gsb(),
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options);
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/* TODO: should identify the error code from internal function execution */
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return CMD_EXEC_SUCCESS;
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}
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/********************************************************************
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* A wrapper function to call the full testbench generator of FPGA-Verilog
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*******************************************************************/
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int write_full_testbench(const OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context) {
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CommandOptionId opt_output_dir = cmd.option("file");
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CommandOptionId opt_bitstream = cmd.option("bitstream");
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CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path");
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CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
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CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
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CommandOptionId opt_fast_configuration = cmd.option("fast_configuration");
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CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
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CommandOptionId opt_default_net_type = cmd.option("default_net_type");
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CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
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CommandOptionId opt_verbose = cmd.option("verbose");
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/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
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* Keep it independent from any other outside data structures
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*/
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VerilogTestbenchOption options;
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options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
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options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
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options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
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options.set_fast_configuration(cmd_context.option_enable(cmd, opt_fast_configuration));
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options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
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options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
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options.set_print_top_testbench(true);
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options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
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if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
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options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));
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}
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/* If pin constraints are enabled by command options, read the file */
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PinConstraints pin_constraints;
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if (true == cmd_context.option_enable(cmd, opt_pcf)) {
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pin_constraints = read_xml_pin_constraints(cmd_context.option_value(cmd, opt_pcf).c_str());
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}
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return fpga_verilog_full_testbench(openfpga_ctx.module_graph(),
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openfpga_ctx.bitstream_manager(),
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openfpga_ctx.fabric_bitstream(),
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g_vpr_ctx.atom(),
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g_vpr_ctx.placement(),
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pin_constraints,
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cmd_context.option_value(cmd, opt_bitstream),
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openfpga_ctx.io_location_map(),
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openfpga_ctx.fabric_global_port_info(),
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openfpga_ctx.vpr_netlist_annotation(),
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openfpga_ctx.arch().circuit_lib,
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openfpga_ctx.simulation_setting(),
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openfpga_ctx.arch().config_protocol,
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options);
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}
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/********************************************************************
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* A wrapper function to call the preconfigured wrapper generator of FPGA-Verilog
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*******************************************************************/
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int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context) {
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CommandOptionId opt_output_dir = cmd.option("file");
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CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path");
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CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
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CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
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CommandOptionId opt_default_net_type = cmd.option("default_net_type");
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CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
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CommandOptionId opt_embed_bitstream = cmd.option("embed_bitstream");
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CommandOptionId opt_verbose = cmd.option("verbose");
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/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
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* Keep it independent from any other outside data structures
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*/
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VerilogTestbenchOption options;
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options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
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options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
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options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
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options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
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options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
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options.set_print_formal_verification_top_netlist(true);
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if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
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options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));
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}
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if (true == cmd_context.option_enable(cmd, opt_embed_bitstream)) {
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options.set_embedded_bitstream_hdl_type(cmd_context.option_value(cmd, opt_embed_bitstream));
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}
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/* If pin constraints are enabled by command options, read the file */
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PinConstraints pin_constraints;
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if (true == cmd_context.option_enable(cmd, opt_pcf)) {
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pin_constraints = read_xml_pin_constraints(cmd_context.option_value(cmd, opt_pcf).c_str());
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}
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return fpga_verilog_preconfigured_fabric_wrapper(openfpga_ctx.module_graph(),
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openfpga_ctx.bitstream_manager(),
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g_vpr_ctx.atom(),
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g_vpr_ctx.placement(),
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pin_constraints,
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openfpga_ctx.io_location_map(),
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openfpga_ctx.fabric_global_port_info(),
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openfpga_ctx.vpr_netlist_annotation(),
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openfpga_ctx.arch().circuit_lib,
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openfpga_ctx.arch().config_protocol,
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options);
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}
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/********************************************************************
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* A wrapper function to call the preconfigured testbench generator of FPGA-Verilog
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*******************************************************************/
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int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context) {
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CommandOptionId opt_output_dir = cmd.option("file");
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CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
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CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path");
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CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
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CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
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CommandOptionId opt_default_net_type = cmd.option("default_net_type");
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CommandOptionId opt_verbose = cmd.option("verbose");
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/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
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* Keep it independent from any other outside data structures
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*/
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VerilogTestbenchOption options;
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options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
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options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
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options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
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options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
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options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
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options.set_print_preconfig_top_testbench(true);
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if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
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options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));
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}
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/* If pin constraints are enabled by command options, read the file */
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PinConstraints pin_constraints;
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if (true == cmd_context.option_enable(cmd, opt_pcf)) {
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pin_constraints = read_xml_pin_constraints(cmd_context.option_value(cmd, opt_pcf).c_str());
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}
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return fpga_verilog_preconfigured_testbench(openfpga_ctx.module_graph(),
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g_vpr_ctx.atom(),
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pin_constraints,
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openfpga_ctx.fabric_global_port_info(),
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openfpga_ctx.vpr_netlist_annotation(),
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openfpga_ctx.simulation_setting(),
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options);
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}
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/********************************************************************
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* A wrapper function to call the simulation task information generator of FPGA-Verilog
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*******************************************************************/
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int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context) {
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CommandOptionId opt_file = cmd.option("file");
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CommandOptionId opt_hdl_dir = cmd.option("hdl_dir");
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CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
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CommandOptionId opt_tb_type = cmd.option("testbench_type");
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CommandOptionId opt_time_unit = cmd.option("time_unit");
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CommandOptionId opt_verbose = cmd.option("verbose");
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/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
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* Keep it independent from any other outside data structures
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*/
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VerilogTestbenchOption options;
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options.set_output_directory(cmd_context.option_value(cmd, opt_hdl_dir));
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options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
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options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
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options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_file));
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if (true == cmd_context.option_enable(cmd, opt_time_unit)) {
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options.set_time_unit(string_to_time_unit(cmd_context.option_value(cmd, opt_time_unit)));
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}
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/* Identify testbench type */
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std::string full_tb_tag("full_testbench");
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std::string preconfig_tb_tag("preconfigured_testbench");
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if (true == cmd_context.option_enable(cmd, opt_tb_type)) {
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if (std::string("preconfigured_testbench") == cmd_context.option_value(cmd, opt_tb_type)) {
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options.set_print_preconfig_top_testbench(true);
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} else if (std::string("full_testbench") == cmd_context.option_value(cmd, opt_tb_type)) {
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options.set_print_preconfig_top_testbench(false);
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options.set_print_top_testbench(true);
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} else {
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/* Invalid option, error out */
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VTR_LOG_ERROR("Invalid option value for testbench type: '%s'! Should be either '%s' or '%s'\n",
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cmd_context.option_value(cmd, opt_tb_type).c_str(),
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full_tb_tag.c_str(),
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preconfig_tb_tag.c_str());
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return CMD_EXEC_FATAL_ERROR;
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}
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} else {
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/* Deposit default type which is the preconfigured testbench */
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options.set_print_preconfig_top_testbench(true);
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}
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return fpga_verilog_simulation_task_info(openfpga_ctx.module_graph(),
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openfpga_ctx.bitstream_manager(),
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g_vpr_ctx.atom(),
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g_vpr_ctx.placement(),
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openfpga_ctx.io_location_map(),
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openfpga_ctx.simulation_setting(),
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openfpga_ctx.arch().config_protocol,
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options);
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}
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} /* end namespace openfpga */
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