72 lines
2.8 KiB
Bash
72 lines
2.8 KiB
Bash
#! /bin/bash
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# Exit if error occurs
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set -e
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# Make sure a clear start
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default_task='lattice_benchmark'
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pwd_path="$PWD"
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task_name=${1:-$default_task} # run task defined in argument else run default task
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config_file="$PWD/configs/${task_name}.conf"
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bench_txt="$PWD/benchmarks/List/${task_name}.txt"
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rpt_file="$PWD/csv_rpts/fpga_spice/${task_name}.csv"
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task_file="$PWD/vpr_fpga_spice_task_lists/${task_name}"
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verilog_path="${PWD}/regression_${task_name}"
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config_file_final=$(echo ${config_file/.conf/_final.conf})
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# List of argument passed to FPGA flow
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vpr_config_flags=(
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'-N 10'
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'-K 6'
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'-ace_d 0.5'
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'-multi_thread 1'
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'-vpr_fpga_x2p_rename_illegal_port'
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'-vpr_fpga_verilog'
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'-vpr_fpga_bitstream_generator'
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'-vpr_fpga_verilog_print_autocheck_top_testbench'
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'-vpr_fpga_verilog_include_timing'
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'-vpr_fpga_verilog_include_signal_init'
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'-vpr_fpga_verilog_formal_verification_top_netlist'
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'-fix_route_chan_width'
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'-vpr_fpga_verilog_include_icarus_simulator'
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'-power'
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)
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# vpr_config_flags+=("$@") # Append provided arguments
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#=============== Argument Sanity Check =====================
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#Check if script running in correct (OpenFPGA/fpga_flow) folder
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if [[ $pwd_path != *"OpenFPGA/fpga_flow"* ]]; then
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echo "Error : Execute script from OpenFPGA/fpga_flow project folder"
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exitflag=1
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fi
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#Check if fconfig and benchmark_list file exists
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for filepath in $config_file $bench_txt; do
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if [ ! -f $filepath ]; then
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echo "$filepath File not found!"
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exitflag=1
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fi
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done
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if [ -n "$exitflag" ]; then
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echo "Terminating script . . . . . . "
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exit 1
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fi
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#=======================================================
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#======== Replace variables in config file =============
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#Extract OpenFPGA Project Path and Escape
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OPENFPGAPATHKEYWORD=$(echo "$(echo $pwd_path | sed 's/.OpenFPGA.*$//')/OpenFPGA" | sed 's/\//\\\//g')
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# Create final config file with replaced keywords replaced variables
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sed 's/OPENFPGAPATHKEYWORD/'"${OPENFPGAPATHKEYWORD}"'/g' $config_file >$config_file_final
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#==================Clean result, change directory and execute ===============
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cd ${pwd_path}/scripts
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# perl fpga_flow.pl -conf ${config_file_final} -benchmark ${bench_txt} -rpt ${rpt_file} -vpr_fpga_verilog_dir $verilog_path $(echo "${vpr_config_flags[@]}")
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perl fpga_flow.pl -conf ${config_file_final} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power
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echo "Netlists successfully generated and simulated"
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exit 0
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