27 lines
576 B
Verilog
27 lines
576 B
Verilog
/////////////////////////////////////////
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// Functionality: A locally generated reset signal which is to test clock network with internal drivers
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// Author: Xifan Tang
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////////////////////////////////////////
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`timescale 1ns / 1ps
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module rst_cond(rst_i, rst_cond_i, clk_i, d_i, q_o);
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input wire rst_cond_i;
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input wire rst_i;
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input wire clk_i;
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input wire d_i;
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output reg q_o;
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wire int_rst;
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assign int_rst = rst_cond_i & rst_i;
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always @(posedge int_rst or posedge clk_i) begin
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if (int_rst) begin
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q_o <= 0;
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end else begin
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q_o <= d_i;
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end
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end
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endmodule
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