53 lines
2.5 KiB
ReStructuredText
53 lines
2.5 KiB
ReStructuredText
.. _file_formats_repack_design_constraints:
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Repack Design Constraints (.xml)
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--------------------------------
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.. warning:: For the best practice, current repack design constraints only support the net remapping between pins in the same port. Pin constraints are **NOT** allowed for two separated ports.
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- A legal pin constraint example: when there are two clock nets, ``clk0`` and ``clk1``, pin constraints are forced on two pins in a clock port ``clk[0:2]`` (e.g., ``clk[0] = clk0`` and ``clk[1] == clk1``).
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- An **illegal** pin constraint example: when there are two clock nets, ``clk0`` and ``clk1``, pin constraints are forced on two clock ports ``clkA[0]`` and ``clkB[0]`` (e.g., ``clkA[0] = clk0`` and ``clkB[0] == clk1``).
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An example of design constraints is shown as follows.
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.. code-block:: xml
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<repack_design_constraints>
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<pin_constraint pb_type="clb" pin="reset[0]" net="rst_n"/>
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<pin_constraint pb_type="clb" pin="clk[0]" net="clk0"/>
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<pin_constraint pb_type="clb" pin="clk[1]" net="clk1"/>
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<pin_constraint pb_type="clb" pin="clk[2]" net="OPEN"/>
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<pin_constraint pb_type="clb" pin="clk[3]" net="OPEN"/>
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<ignore_net name="rst_n" pin="clb.I[0:11]"/>
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</repack_design_constraints>
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Pin constraint
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^^^^^^^^^^^^^^
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.. option:: pb_type="<string>"
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The pb_type name to be constrained, which should be consistent with VPR's architecture description.
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.. option:: pin="<string>"
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The pin name of the ``pb_type`` to be constrained, which should be consistent with VPR's architecture description.
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.. option:: net="<string>"
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The net name of the pin to be mapped, which should be consistent with net definition in your ``.blif`` file. The reserved word ``OPEN`` means that no net should be mapped to a given pin. Please ensure that it is not conflicted with any net names in your ``.blif`` file.
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.. warning:: Design constraints is a feature for power-users. It may cause repack to fail. It is users's responsibility to ensure proper design constraints
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Ignore net
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^^^^^^^^^^
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To ignore the global nets on specific pins, use the syntax ``ignore_net``. Note that the qualified pins are inputs, outputs, and clocks of pb_type. The option is useful for preventing global nets from being assigned to unwanted pins on pb_type.
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.. option:: name="<string>"
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The global nets's name to be ignored, which should be consistent with user-defined global nets in the PCF file.
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.. option:: pin="<string>"
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The specified pins on a certain programmable block, which should be consistent with VPR's architecture description.
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