tangxifan 6f42aac626 add wire connection in Verilog module declaration		2019-10-08 20:14:38 -06:00
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libarchfpga	refactored counting config bits for circuit model and update Verilog generation for primitive pb_types	2019-10-08 18:00:04 -06:00
libpcre	update travis configuration and clean up repository	2019-06-07 22:19:11 -06:00
libprinthandler	update travis configuration and clean up repository	2019-06-07 22:19:11 -06:00
vpr	add wire connection in Verilog module declaration	2019-10-08 20:14:38 -06:00
CMakeLists.txt	Add latest abc and update ace dependence	2019-05-03 18:56:03 -06:00