OpenFPGA/vpr
tangxifan 07e1979498 add architecture examples on wide memory blocks (width=2). tileable routing is working 2020-03-28 15:41:26 -06:00
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scripts add vpr8 libs and core engine for further integration 2020-01-03 16:14:42 -07:00
src add architecture examples on wide memory blocks (width=2). tileable routing is working 2020-03-28 15:41:26 -06:00
test add vpr8 libs and core engine for further integration 2020-01-03 16:14:42 -07:00
CMakeLists.txt move rr_gsb and rr_chan to tileable rr_graph builder 2020-03-04 14:14:28 -07:00
main.ui add vpr8 libs and core engine for further integration 2020-01-03 16:14:42 -07:00
valgrind.supp bring RRGraph object and writer online 2020-01-31 16:39:40 -07:00
vpr add vpr8 libs and core engine for further integration 2020-01-03 16:14:42 -07:00