tangxifan 2f38b5cbc2 Merge branch 'refactoring' into dev		2020-03-08 16:23:20 -06:00
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SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	Adding heterogeneous synthesis requirements	2019-12-03 16:09:26 -07:00
arch	hotfix on removing dangling inputs from GSB, which are CLB direct output	2020-03-08 13:54:49 -06:00
benchmarks	passing regression test on dpram benchmarks	2019-11-07 14:57:46 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Adding heterogeneous synthesis requirements	2019-12-03 16:09:26 -07:00
scripts	Added disp option in openfpga_flow, Default is --nodisp	2020-01-23 10:04:38 -07:00
tasks	Add compilation verification task in openfpga_flow	2020-01-23 13:13:23 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00