tangxifan 6eb125ec2a Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML		2020-04-06 14:09:52 -06:00
..
src	bug fixing in Verilog top-level testbench generation	2020-04-05 17:50:11 -06:00
test_blif	add missing files for micro benchmarks	2020-03-20 11:08:55 -06:00
test_openfpga_arch	Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML	2020-04-06 14:09:52 -06:00
test_script	Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML	2020-04-06 14:09:52 -06:00
test_vpr_arch	added FPGA architecture with I/Os on the left and right sides	2020-04-01 15:46:38 -06:00
CMakeLists.txt	add simulation ini file writer	2020-02-27 18:01:47 -07:00