tangxifan 2ef083c49d adapt SB module builder to use bus ports		2020-06-30 16:02:40 -06:00
..
analysis	add vpr8 libs and core engine for further integration	2020-01-03 16:14:42 -07:00
base	reduce activity error to warning.	2020-04-22 17:36:02 -06:00
device	minor fix on rr_graph.clear()	2020-03-27 11:26:14 -06:00
draw	correct missing rr_nodes usage to rr_graph obj	2020-02-04 16:48:15 -07:00
pack	bug fix in packable mode support	2020-06-11 19:31:07 -06:00
place	bug fixing for heterogenenous FPGA when using the RRGraph object	2020-02-04 17:31:39 -07:00
power	power estimation adapted to use RRGraph object	2020-02-01 12:26:42 -07:00
route	update print_route() in VPR to show correct track_id when tileable routing is used	2020-03-25 17:55:28 -06:00
tileable_rr_graph	adapt SB module builder to use bus ports	2020-06-30 16:02:40 -06:00
timing	net delay adopt RRGraph object, compile with no errors	2020-02-01 22:38:21 -07:00
util	correct missing rr_nodes usage to rr_graph obj	2020-02-04 16:48:15 -07:00
main.cpp	add vpr8 libs and core engine for further integration	2020-01-03 16:14:42 -07:00