133 lines
6.7 KiB
ReStructuredText
133 lines
6.7 KiB
ReStructuredText
.. _fabric_netlists:
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Fabric Netlists
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---------------
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In this part, we will introduce the hierarchy, dependency and functionality of each Verilog netlist, which are generated to model the FPGA fabric.
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.. note:: These netlists are automatically generated by the OpenFPGA command ``write_fabric_verilog``. See :ref:`openfpga_verilog_commands` for its detailed usage.
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All the generated Verilog netlists are located in the directory as you specify in the OpenFPGA command ``write_fabric_verilog``.
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Inside the directory, the Verilog netlists are organized as illustrated in :numref:`fig_fabric_netlist_hierarchy`.
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.. _fig_fabric_netlist_hierarchy:
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.. figure:: ./figures/fabric_netlist_hierarchy.png
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:scale: 90%
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Hierarchy of Verilog netlists modeling a FPGA fabric
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.. _fig_generic_fabric:
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.. figure:: ./figures/generic_fabric.png
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:scale: 80%
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An illustrative FPGA fabric modelled by the Verilog netlists
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Top-level Netlists
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~~~~~~~~~~~~~~~~~~
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.. option:: fabric_netlists.v
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This file includes all the related Verilog netlists that are used by the ``fpga_top.v``.
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This file is created to simplify the netlist addition for HDL simulator and backend tools.
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This is the only file you need to add to a simulator or backend project.
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.. note:: User-defined (external) Verilog netlists are included in this file.
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.. option:: fpga_top.v
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This netlist contains the top-level module of the fpga fabric, corresponding to the fabric shown in :numref:`fig_generic_fabric`.
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.. option:: fpga_defines.v
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This file includes pre-processing flags required by the ``fpga_top.v``, to smooth HDL simulation.
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It will include the folliwng pre-procesing flags:
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- ```define ENABLE_TIMING`` When enabled, all the delay values defined in primitive Verilog modules will be considered in compilation. This flag is added when ``--include_timing`` option is enabled when calling the ``write_fabric_verilog`` command.
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.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
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- ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_fabric_verilog`` command.
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.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
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- ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_fabric_verilog`` command.
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.. warning:: Please disable this flag if you are not using icarus iVerilog simulator.
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__ iverilog_website_
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.. _iverilog_website: http://iverilog.icarus.com/
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Logic Blocks
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~~~~~~~~~~~~
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This sub-directory contains all the Verilog modules modeling configurable logic blocks, heterogeneous blocks as well as I/O blocks.
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Take the example in :numref:`fig_generic_fabric`, the modules are CLBs, DSP blocks, I/Os and Block RAMs.
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.. option:: <physical_tile_name>.v
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For each ``<physical_tile>`` defined in the VPR architecture description, a Verilog netlist will be generated to model its internal structure.
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.. note:: For I/O blocks, separated ``<physical_tile_name>.v`` will be generated for each side of a FPGA fabric.
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.. option:: <logical_tile_name>.v
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For each root ``pb_type`` defined in the ``<complexblock>`` of VPR architecture description, a Verilog netlist will be generated to model its internal structure.
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Routing Blocks
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~~~~~~~~~~~~~~
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This sub-directory contains all the Verilog modules modeling Switch Blocks (SBs) and Connection Blocks (CBs).
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Take the example in :numref:`fig_generic_fabric`, the modules are the Switch Blocks, X- and Y- Connection Blocks of a tile.
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.. option:: sb_<x>_<y>.v
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For each unique Switch Block (SB) created by VPR routing resource graph generator, a Verilog netlist will be generated. The ``<x>`` and ``<y>`` denote the coordinate of the Switch Block in the FPGA fabric.
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.. option:: cbx_<x>_<y>.v
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For each unique X-direction Connection Block (CBX) created by VPR routing resource graph generator, a Verilog netlist will be generated. The ``<x>`` and ``<y>`` denote the coordinate of the Connection Block in the FPGA fabric.
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.. option:: cby_<x>_<y>.v
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For each unique Y-direction Connection Block (CBY) created by VPR routing resource graph generator, a Verilog netlist will be generated. The ``<x>`` and ``<y>`` denote the coordinate of the Connection Block in the FPGA fabric.
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Primitive Modules
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~~~~~~~~~~~~~~~~~
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This sub-directory contains all the primitive Verilog modules, which are used to build the logic blocks and routing blocks.
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.. option:: luts.v
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Verilog modules for all the Look-Up Tables (LUTs), which are defined as ``<circuit_model name="lut">`` of OpenFPGA architecture description. See details in :ref:`circuit_library`.
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.. option:: wires.v
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Verilog modules for all the routing wires, which are defined as ``<circuit_model name="wire|chan_wire">`` of OpenFPGA architecture description. See details in :ref:`circuit_library`.
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.. option:: memories.v
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Verilog modules for all the configurable memories, which are defined as ``<circuit_model name="ccff|sram">`` of OpenFPGA architecture description. See details in :ref:`circuit_library`.
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.. option:: muxes.v
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Verilog modules for all the routing multiplexers, which are defined as ``<circuit_model name="mux">`` of OpenFPGA architecture description. See details in :ref:`circuit_library`.
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.. note:: multiplexers used in Look-Up Tables are also defined in this netlist.
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.. option:: inv_buf_passgate.v
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Verilog modules for all the inverters, buffers and pass-gate logics, which are defined as ``<circuit_model name="inv_buf|pass_gate">`` of OpenFPGA architecture description. See details in :ref:`circuit_library`.
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.. option:: local_encoder.v
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Verilog modules for all the encoders and decoders, which are created when routing multiplexers are defined to include local encoders. See details in :ref:`circuit_model_examples`.
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.. option:: user_defined_templates.v
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This is a template netlist, which users can refer to when writing up their user-defined Verilog modules.
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The user-defined Verilog modules are those ``<circuit_model>`` in the OpenFPGA architecture description with a specific ``verilog_netlist`` path.
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It contains Verilog modules with ports declaration (compatible to other netlists that are auto-generated by OpenFPGA) but without any functionality.
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This file is created only when the option ``--print_user_defined_template`` is enabled when calling the ``write_fabric_verilog`` command.
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.. warning:: Do not include this netlist in simulation without any modification to its content!
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