41 lines
966 B
Verilog
41 lines
966 B
Verilog
//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Verilog Decoders
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// Author: Xifan TANG
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// Organization: EPFL/IC/LSI
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// Date: Thu Nov 15 14:26:04 2018
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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//----- BL Decoder convert 5 bits to binary 19 bits -----
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module bl_decoder5to19 (
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input wire enable,
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input wire [4:0] addr_in,
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input wire data_in,
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output reg [0:18] addr_out
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);
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always@(addr_out,addr_in,enable, data_in)
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begin
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addr_out = 19'bz;
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if (1'b1 == enable) begin
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addr_out[addr_in] = data_in;
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end
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end
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endmodule
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//----- WL Decoder convert 5 bits to binary 19 bits -----
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module wl_decoder5to19 (
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input wire enable,
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input wire [4:0] addr_in,
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output reg [0:18] addr_out
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);
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always@(addr_out,addr_in,enable)
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begin
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addr_out = 19'b0;
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if (1'b1 == enable) begin
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addr_out[addr_in] = 1'b1;
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end
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end
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endmodule
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