tangxifan 6e1b58f8a6 [Tool] Update FPGA-Verilog testbench generator to accept pin constraints to non-clock global ports		2021-04-17 15:05:22 -06:00
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src	[Tool] Update FPGA-Verilog testbench generator to accept pin constraints to non-clock global ports	2021-04-17 15:05:22 -06:00
CMakeLists.txt	[Tool] Deploy pin constraints to preconfig Verilog module generation	2021-01-19 16:56:30 -07:00