921 lines
41 KiB
Python
921 lines
41 KiB
Python
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Script Name : run_fpga_flow.py
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# Description : This script designed to run different flows supported by
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# OpensFPGA project.
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# Args : python3 run_fpga_flow.py --help
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# Author : Ganesh Gore
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# Email : ganesh.gore@utah.edu
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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import os
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import sys
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import shutil
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import time
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import traceback
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from datetime import timedelta
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import shlex
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import glob
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import json
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import argparse
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from configparser import ConfigParser, ExtendedInterpolation
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import logging
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from envyaml import EnvYAML
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import glob
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import subprocess
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import threading
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from string import Template
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import re
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import xml.etree.ElementTree as ET
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from importlib import util
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if util.find_spec("humanize"):
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import humanize
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if sys.version_info[0] < 3:
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raise Exception("run_fpga_task script must be using Python 3")
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Initialise general paths for the script
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Copy directory where flow file exist
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flow_script_dir = os.path.dirname(os.path.abspath(__file__))
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# Find OpenFPGA base directory
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openfpga_base_dir = os.path.abspath(
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os.path.join(flow_script_dir, os.pardir, os.pardir))
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# Copy directory from where script is laucnhed
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# [req to resolve relative paths provided while launching script]
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launch_dir = os.getcwd()
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# Path section to append in configuration file to interpolate path
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task_script_dir = os.path.dirname(os.path.abspath(__file__))
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script_env_vars = ({"PATH": {
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"OPENFPGA_FLOW_PATH": task_script_dir,
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"ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "arch"),
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"OPENFPGA_SHELLSCRIPT_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "OpenFPGAShellScripts"),
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"BENCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "benchmarks"),
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"TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "tech"),
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"SPICENETLIST_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "SpiceNetlists"),
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"VERILOG_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "VerilogNetlists"),
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"OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir,
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os.pardir))}})
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Reading command-line argument
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Helper function to provide better alignment to help print
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def formatter(prog): return argparse.HelpFormatter(prog, max_help_position=60)
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parser = argparse.ArgumentParser(formatter_class=formatter)
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# Mandatory arguments
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parser.add_argument('arch_file', type=str)
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parser.add_argument('benchmark_files', type=str, nargs='+')
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# parser.add_argument('extraArgs', nargs=argparse.REMAINDER)
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parser.add_argument('otherthings', nargs='*')
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# Optional arguments
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parser.add_argument('--top_module', type=str, default="top")
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parser.add_argument('--fpga_flow', type=str, default="yosys_vpr")
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parser.add_argument('--flow_config', type=str,
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help="CAD tools path overrides default setting")
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parser.add_argument('--run_dir', type=str,
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default=os.path.join(openfpga_base_dir, 'tmp'),
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help="Directory to store intermidiate file & final results")
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parser.add_argument('--openfpga_shell_template', type=str,
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default=os.path.join("openfpga_flow",
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"openfpga_shell_scripts",
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"example_script.openfpga"),
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help="Sample openfpga shell script")
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parser.add_argument('--openfpga_arch_file', type=str,
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help="Openfpga architecture file for shell")
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parser.add_argument('--arch_variable_file', type=str, default=None,
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help="Openfpga architecture file for shell")
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# parser.add_argument('--openfpga_sim_setting_file', type=str,
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# help="Openfpga simulation file for shell")
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# parser.add_argument('--external_fabric_key_file', type=str,
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# help="Key file for shell")
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parser.add_argument('--yosys_tmpl', type=str, default=None,
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help="Alternate yosys template, generates top_module.blif")
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parser.add_argument('--ys_rewrite_tmpl', type=str, default=None,
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help="Alternate yosys template, to rewrite verilog netlist")
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parser.add_argument('--verific', action="store_true",
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help="Run yosys with verific enabled")
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parser.add_argument('--disp', action="store_true",
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help="Open display while running VPR")
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parser.add_argument('--debug', action="store_true",
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help="Run script in debug mode")
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# Blif_VPR Only flow arguments
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parser.add_argument('--activity_file', type=str,
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help="Activity file used while running yosys flow")
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parser.add_argument('--base_verilog', type=str,
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help="Original Verilog file to run verification in " +
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"blif_VPR flow")
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# ACE2 and power estimation related arguments
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parser.add_argument('--K', type=int,
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help="LUT Size, if not specified extracted from arch file")
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parser.add_argument('--power', action='store_true')
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parser.add_argument('--power_tech', type=str,
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help="Power tech xml file for power calculation")
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parser.add_argument('--ace_d', type=float,
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help="Specify the default signal density of PIs in ACE2")
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parser.add_argument('--ace_p', type=float,
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help="Specify the default signal probablity of PIs in ACE2")
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parser.add_argument('--black_box_ace', action='store_true')
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# VPR Options
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parser.add_argument('--min_route_chan_width', type=float,
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help="Turn on min_route_chan_width")
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parser.add_argument('--max_route_width_retry', type=int, default=100,
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help="Maximum iterations to perform to reroute")
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parser.add_argument('--fix_route_chan_width', type=int,
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help="Turn on fix_route_chan_width")
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parser.add_argument('--vpr_timing_pack_off', action='store_true',
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help="Turn off the timing-driven pack for vpr")
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parser.add_argument('--vpr_place_clb_pin_remap', action='store_true',
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help="Turn on place_clb_pin_remap in VPR")
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parser.add_argument('--vpr_max_router_iteration', type=int,
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help="Specify the max router iteration in VPR")
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parser.add_argument('--vpr_route_breadthfirst', action='store_true',
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help="Use the breadth-first routing algorithm of VPR")
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parser.add_argument('--vpr_use_tileable_route_chan_width', action='store_true',
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help="Turn on the conversion to " +
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"tileable_route_chan_width in VPR")
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# VPR - FPGA-X2P Extension
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X2PParse = parser.add_argument_group('VPR-FPGA-X2P Extension')
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X2PParse.add_argument('--vpr_fpga_x2p_rename_illegal_port', action='store_true',
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help="Rename illegal ports option of VPR FPGA SPICE")
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X2PParse.add_argument('--vpr_fpga_x2p_signal_density_weight', type=float,
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help="Specify the signal_density_weight of VPR FPGA SPICE")
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X2PParse.add_argument('--vpr_fpga_x2p_sim_window_size', type=float,
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help="specify the sim_window_size of VPR FPGA SPICE")
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X2PParse.add_argument('--vpr_fpga_x2p_compact_routing_hierarchy',
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action="store_true", help="Compact_routing_hierarchy")
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X2PParse.add_argument('--vpr_fpga_x2p_duplicate_grid_pin', action="store_true",
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help="Added duplicated grid pin")
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# VPR - FPGA-SPICE Extension
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SPParse = parser.add_argument_group('FPGA-SPICE Extension')
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SPParse.add_argument('--vpr_fpga_spice', action='store_true',
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help="Print SPICE netlists in VPR")
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SPParse.add_argument('--vpr_fpga_spice_sim_mt_num', type=int,
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help="Specify the option sim_mt_num of VPR FPGA SPICE")
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SPParse.add_argument('--vpr_fpga_spice_print_component_tb', action='store_true',
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help="Output component-level testbench")
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SPParse.add_argument('--vpr_fpga_spice_print_grid_tb', action='store_true',
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help="Output grid-level testbench")
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SPParse.add_argument('--vpr_fpga_spice_print_top_testbench', action='store_true',
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help="Output full-chip-level testbench")
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SPParse.add_argument('--vpr_fpga_spice_leakage_only', action='store_true',
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help="Turn on leakage_only mode in VPR FPGA SPICE")
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SPParse.add_argument('--vpr_fpga_spice_parasitic_net_estimation_off',
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action='store_true',
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help="Turn off parasitic_net_estimation in VPR FPGA SPICE")
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SPParse.add_argument('--vpr_fpga_spice_testbench_load_extraction_off',
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action='store_true',
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help="Turn off testbench_load_extraction in VPR FPGA SPICE")
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SPParse.add_argument('--vpr_fpga_spice_simulator_path', type=str,
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help="Specify simulator path")
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# VPR - FPGA-Verilog Extension
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VeriPar = parser.add_argument_group('FPGA-Verilog Extension')
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VeriPar.add_argument('--vpr_fpga_verilog', action='store_true',
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help="Generator verilog of VPR FPGA SPICE")
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VeriPar.add_argument('--vpr_fpga_verilog_dir', type=str,
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help="path to store generated verilog files")
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VeriPar.add_argument('--vpr_fpga_verilog_include_timing', action="store_true",
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help="Print delay specification in Verilog files")
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VeriPar.add_argument('--vpr_fpga_verilog_include_signal_init',
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action="store_true",
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help="Print signal initialization in Verilog files")
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VeriPar.add_argument('--vpr_fpga_verilog_print_autocheck_top_testbench',
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action="store_true", help="Print autochecked top-level " +
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"testbench for Verilog Generator of VPR FPGA SPICE")
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VeriPar.add_argument('--vpr_fpga_verilog_formal_verification_top_netlist',
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action="store_true", help="Print formal top Verilog files")
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VeriPar.add_argument('--vpr_fpga_verilog_include_icarus_simulator',
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action="store_true", help="dd syntax and definition" +
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" required to use Icarus Verilog simulator")
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VeriPar.add_argument('--vpr_fpga_verilog_print_user_defined_template',
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action="store_true", help="Unknown parameter")
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VeriPar.add_argument('--vpr_fpga_verilog_print_report_timing_tcl',
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action="store_true", help="Generate tcl script useful " +
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"for timing report generation")
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VeriPar.add_argument('--vpr_fpga_verilog_report_timing_rpt_path',
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type=str, help="Specify path for report timing results")
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VeriPar.add_argument('--vpr_fpga_verilog_print_sdc_pnr', action="store_true",
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help="Generate sdc file to constraint Hardware P&R")
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VeriPar.add_argument('--vpr_fpga_verilog_print_sdc_analysis',
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action="store_true", help="Generate sdc file to do STA")
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VeriPar.add_argument('--vpr_fpga_verilog_print_top_tb', action="store_true",
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help="Print top-level testbench for Verilog Generator " +
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"of VPR FPGA SPICE")
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VeriPar.add_argument('--vpr_fpga_verilog_print_input_blif_tb',
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action="store_true", help="Print testbench" +
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"for input blif file in Verilog Generator")
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VeriPar.add_argument('--vpr_fpga_verilog_print_simulation_ini', action="store_true",
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help="Create simulation INI file")
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VeriPar.add_argument('--vpr_fpga_verilog_explicit_mapping', action="store_true",
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help="Explicit Mapping")
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# VPR - FPGA-Bitstream Extension
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BSparse = parser.add_argument_group('FPGA-Bitstream Extension')
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BSparse.add_argument('--vpr_fpga_bitstream_generator', action="store_true",
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help="Generate FPGA-SPICE bitstream")
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# Regression test option
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RegParse = parser.add_argument_group('Regression Test Extension')
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RegParse.add_argument("--end_flow_with_test", action="store_true",
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help="Run verification test at the end")
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Global varaibles declaration
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Setting up print and logging system
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logging.basicConfig(level=logging.INFO, stream=sys.stdout,
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format='%(levelname)s - %(message)s')
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logger = logging.getLogger('OpenFPGA_Flow_Logs')
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# variable to store script_configuration and cad tool paths
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config, cad_tools = None, None
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ExecTime = {}
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Main program starts here
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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def main():
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logger.debug("Script Launched in "+os.getcwd())
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check_required_file()
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read_script_config()
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validate_command_line_arguments()
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prepare_run_directory(args.run_dir)
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if (args.fpga_flow == "yosys_vpr"):
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logger.info('Running "yosys_vpr" Flow')
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run_yosys_with_abc()
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# TODO Make it optional if activity file is provided
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if args.power:
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run_ace2()
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run_pro_blif_3arg()
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else:
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# Make a copy of the blif file to be compatible with vpr flow
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shutil.copy(args.top_module+'_yosys_out.blif', args.top_module+".blif")
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# Always Generate the post-synthesis verilog files
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run_rewrite_verilog()
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if (args.fpga_flow == "vpr_blif"):
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collect_files_for_vpr()
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if (args.fpga_flow == "yosys"):
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run_yosys_with_abc()
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if not (args.fpga_flow == "yosys"):
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logger.info("Running OpenFPGA Shell Engine ")
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run_openfpga_shell()
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if args.end_flow_with_test:
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run_netlists_verification()
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ExecTime["End"] = time.time()
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def timestr(x): return humanize.naturaldelta(timedelta(seconds=x)) \
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if "humanize" in sys.modules else str(int(x)) + " Sec "
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if (args.fpga_flow == "yosys"):
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TimeInfo = ("Openfpga_flow completed, " +
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"Total Time Taken %s " %
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timestr(ExecTime["End"]-ExecTime["Start"]))
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else:
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TimeInfo = ("Openfpga_flow completed, " +
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"Total Time Taken %s " %
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timestr(ExecTime["End"]-ExecTime["Start"]) +
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"VPR Time %s " %
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timestr(ExecTime["VPREnd"]-ExecTime["VPRStart"]))
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TimeInfo += ("Verification Time %s " %
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timestr(ExecTime["VerificationEnd"] -
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ExecTime["VerificationStart"])
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if args.end_flow_with_test else "")
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logger.info(TimeInfo)
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exit()
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Subroutines starts here
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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def check_required_file():
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""" Function ensure existace of all required files for the script """
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files_dict = {
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"CAD TOOL PATH": os.path.join(flow_script_dir, os.pardir, 'misc',
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'fpgaflow_default_tool_path.conf'),
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}
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for filename, filepath in files_dict.items():
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if not os.path.isfile(filepath):
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clean_up_and_exit("Not able to locate default file " + filename)
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def read_script_config():
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""" This fucntion reads default CAD tools path from configuration file """
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global config, cad_tools
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config = ConfigParser(interpolation=ExtendedInterpolation())
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config.read_dict(script_env_vars)
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default_cad_tool_conf = os.path.join(flow_script_dir, os.pardir, 'misc',
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'fpgaflow_default_tool_path.conf')
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config.read_file(open(default_cad_tool_conf))
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if args.flow_config:
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config.read_file(open(args.flow_config))
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if not "CAD_TOOLS_PATH" in config.sections():
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clean_up_and_exit("Missing CAD_TOOLS_PATH in openfpga_flow config")
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cad_tools = config["CAD_TOOLS_PATH"]
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if args.arch_variable_file:
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_, file_extension = os.path.splitext(args.arch_variable_file)
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if file_extension in [".yml", ".yaml"]:
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script_env_vars["PATH"].update(
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EnvYAML(args.arch_variable_file, include_environment=False))
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if file_extension in [".json", ]:
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with open(args.arch_variable_file, "r") as fp:
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script_env_vars["PATH"].update(json.load(fp))
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def validate_command_line_arguments():
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'''
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This function validate the command line arguments
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FLOW_SCRIPT_CONFIG->valid_flows :
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Key is used to validate if the request flow is supported by the script
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CMD_ARGUMENT_DEPENDANCY :
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Validates the dependencies of the command arguments
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Checks the following file exists and replaces them with an absolute path
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- All architecture files
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- Benchmark files
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- Power tech files
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- Run directory
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- Activity file
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- Base verilog file
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'''
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logger.info("Validating command line arguments")
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if args.debug:
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logger.info("Setting loggger in debug mode")
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logger.setLevel(logging.DEBUG)
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# Check if flow supported
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if not args.fpga_flow in config.get("FLOW_SCRIPT_CONFIG", "valid_flows"):
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clean_up_and_exit("%s Flow not supported" % args.fpga_flow)
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# Check if argument list is consistant
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for eacharg, dependent in config.items("CMD_ARGUMENT_DEPENDANCY"):
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if getattr(args, eacharg, None):
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dependent = dependent.split(",")
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for eachdep in dependent:
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if not any([getattr(args, i, 0) for i in eachdep.split("|")]):
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clean_up_and_exit("'%s' argument depends on (%s) arguments" %
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(eacharg, ", ".join(dependent).replace("|", " or ")))
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# Check if architecrue files exists
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args.arch_file = os.path.abspath(args.arch_file)
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if not os.path.isfile(args.arch_file):
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clean_up_and_exit(
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"VPR architecture file not found. -%s"%
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args.arch_file)
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args.openfpga_arch_file = os.path.abspath(args.openfpga_arch_file)
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if not os.path.isfile(args.openfpga_arch_file):
|
|
clean_up_and_exit(
|
|
"OpenFPGA architecture file not found. -%s"%
|
|
args.openfpga_arch_file)
|
|
|
|
# Filter provided benchmark files
|
|
for index, everyinput in enumerate(args.benchmark_files):
|
|
args.benchmark_files[index] = os.path.abspath(everyinput)
|
|
if os.path.isdir(args.benchmark_files[index]):
|
|
logger.warning("Skipping directory in bench %s" % everyinput)
|
|
logger.warning("Directory is not support in benchmark list" +
|
|
"use wildcard pattern to add files")
|
|
continue
|
|
for everyfile in glob.glob(args.benchmark_files[index]):
|
|
if not os.path.isfile(everyfile):
|
|
clean_up_and_exit(
|
|
"Failed to copy benchmark file -%s" % args.arch_file)
|
|
|
|
# Filter provided powertech files
|
|
if args.power_tech:
|
|
args.power_tech = os.path.abspath(args.power_tech)
|
|
if not os.path.isfile(args.power_tech):
|
|
clean_up_and_exit(
|
|
"Power Tech file not found. -%s" % args.power_tech)
|
|
|
|
# Expand run directory to absolute path
|
|
args.run_dir = os.path.abspath(args.run_dir)
|
|
if args.power:
|
|
if args.activity_file:
|
|
args.activity_file = os.path.abspath(args.activity_file)
|
|
if args.base_verilog:
|
|
args.base_verilog = os.path.abspath(args.base_verilog)
|
|
|
|
|
|
def prepare_run_directory(run_dir):
|
|
"""
|
|
Prepares run directory to run
|
|
1. Change current directory to run_dir
|
|
2. Copy architecture XML file to run_dir
|
|
3. Copy circuit files to run_dir
|
|
"""
|
|
logger.info("Run directory : %s" % run_dir)
|
|
if os.path.isdir(run_dir):
|
|
no_of_files = len(next(os.walk(run_dir))[2])
|
|
shutil.rmtree(run_dir)
|
|
os.makedirs(run_dir)
|
|
# Clean run_dir is created change working directory
|
|
os.chdir(run_dir)
|
|
|
|
# Create arch dir in run_dir and copy flattened architecture file
|
|
os.mkdir("arch")
|
|
tmpl = Template(
|
|
open(args.arch_file, encoding='utf-8').read())
|
|
arch_filename = os.path.basename(args.arch_file)
|
|
args.arch_file = os.path.join(run_dir, "arch", arch_filename)
|
|
with open(args.arch_file, 'w', encoding='utf-8') as archfile:
|
|
archfile.write(tmpl.safe_substitute(script_env_vars["PATH"]))
|
|
|
|
if (args.openfpga_arch_file):
|
|
tmpl = Template(
|
|
open(args.openfpga_arch_file, encoding='utf-8').read())
|
|
arch_filename = os.path.basename(args.openfpga_arch_file)
|
|
args.openfpga_arch_file = os.path.join(run_dir, "arch", arch_filename)
|
|
with open(args.openfpga_arch_file, 'w', encoding='utf-8') as archfile:
|
|
archfile.write(tmpl.safe_substitute(script_env_vars["PATH"]))
|
|
|
|
# Sanitize provided openshell template, if provided
|
|
if (args.openfpga_shell_template):
|
|
if not os.path.isfile(args.openfpga_shell_template or ""):
|
|
logger.error("Openfpga shell file - %s" %
|
|
args.openfpga_shell_template)
|
|
clean_up_and_exit("Provided openfpga_shell_template" +
|
|
f" {args.openfpga_shell_template} file not found")
|
|
else:
|
|
shutil.copy(args.openfpga_shell_template,
|
|
args.top_module+"_template.openfpga")
|
|
|
|
# Create benchmark dir in run_dir and copy flattern architecture file
|
|
os.mkdir("benchmark")
|
|
try:
|
|
for index, eachfile in enumerate(args.benchmark_files):
|
|
args.benchmark_files[index] = shutil.copy2(
|
|
eachfile, os.path.join(os.curdir, "benchmark"))
|
|
except:
|
|
logger.exception("Failed to copy all benchmark file to run_dir")
|
|
|
|
|
|
def clean_up_and_exit(msg, clean=False):
|
|
logger.error("Current working directory : " + os.getcwd())
|
|
logger.error(msg)
|
|
logger.error("Exiting . . . . . .")
|
|
exit(1)
|
|
|
|
def create_yosys_params():
|
|
tree = ET.parse(args.arch_file)
|
|
root = tree.getroot()
|
|
try:
|
|
lut_size = max([int(pb_type.find("input").get("num_pins"))
|
|
for pb_type in root.iter("pb_type")
|
|
if pb_type.get("class") == "lut"])
|
|
logger.info("Extracted lut_size size from arch XML = %s", lut_size)
|
|
logger.info("Running Yosys with lut_size = %s", lut_size)
|
|
except:
|
|
logger.exception("Failed to extract lut_size from XML file")
|
|
clean_up_and_exit("")
|
|
args.K = lut_size
|
|
# Yosys script parameter mapping
|
|
ys_params = script_env_vars["PATH"]
|
|
|
|
for indx in range(0, len(OpenFPGAArgs), 2):
|
|
tmpVar = OpenFPGAArgs[indx][2:].upper()
|
|
ys_params[tmpVar] = OpenFPGAArgs[indx+1]
|
|
|
|
if not args.verific:
|
|
ys_params["VERILOG_FILES"] = " ".join([
|
|
shlex.quote(eachfile) for eachfile in args.benchmark_files])
|
|
if not "READ_VERILOG_OPTIONS" in ys_params:
|
|
ys_params["READ_VERILOG_OPTIONS"] = ""
|
|
else:
|
|
if "ADD_INCLUDE_DIR" not in ys_params:
|
|
ys_params["ADD_INCLUDE_DIR"] = ""
|
|
if "ADD_LIBRARY_DIR" not in ys_params:
|
|
ys_params["ADD_LIBRARY_DIR"] = ""
|
|
if "ADD_BLACKBOX_MODULES" not in ys_params:
|
|
ys_params["ADD_BLACKBOX_MODULES"] = ""
|
|
if "READ_HDL_FILE" not in ys_params:
|
|
ys_params["READ_HDL_FILE"] = ""
|
|
if "READ_LIBRARY" not in ys_params:
|
|
ys_params["READ_LIBRARY"] = ""
|
|
if "VERIFIC_VERILOG_STANDARD" not in ys_params:
|
|
ys_params["VERIFIC_VERILOG_STANDARD"] = "-vlog2k"
|
|
if "VERIFIC_SYSTEMVERILOG_STANDARD" not in ys_params:
|
|
ys_params["VERIFIC_SYSTEMVERILOG_STANDARD"] = "-sv"
|
|
if "VERIFIC_VHDL_STANDARD" not in ys_params:
|
|
ys_params["VERIFIC_VHDL_STANDARD"] = "-vhdl"
|
|
ext_to_standard_map = {
|
|
".v" : ys_params["VERIFIC_VERILOG_STANDARD"],
|
|
".vh" : ys_params["VERIFIC_VERILOG_STANDARD"],
|
|
".verilog" : ys_params["VERIFIC_VERILOG_STANDARD"],
|
|
".vlg" : ys_params["VERIFIC_VERILOG_STANDARD"],
|
|
".sv" : ys_params["VERIFIC_SYSTEMVERILOG_STANDARD"],
|
|
".svh" : ys_params["VERIFIC_SYSTEMVERILOG_STANDARD"],
|
|
".vhd" : ys_params["VERIFIC_VHDL_STANDARD"],
|
|
".vhdl" : ys_params["VERIFIC_VHDL_STANDARD"]
|
|
}
|
|
lib_files = []
|
|
include_dirs = set([os.path.dirname(eachfile) for eachfile in args.benchmark_files])
|
|
if "VERIFIC_INCLUDE_DIR" in ys_params:
|
|
include_dirs.update(ys_params["VERIFIC_INCLUDE_DIR"].split(","))
|
|
if include_dirs and not ys_params["ADD_INCLUDE_DIR"]:
|
|
ys_params["ADD_INCLUDE_DIR"] = "\n".join(["verific -vlog-incdir " +
|
|
shlex.quote(eachdir) for eachdir in include_dirs])
|
|
if "VERIFIC_LIBRARY_DIR" in ys_params:
|
|
ys_params["ADD_LIBRARY_DIR"] = "\n".join(["verific -vlog-libdir " +
|
|
shlex.quote(eachdir) for eachdir in ys_params["VERIFIC_LIBRARY_DIR"].split(",")])
|
|
try:
|
|
for param, value in ys_params.items():
|
|
if param.startswith("VERIFIC_READ_LIB_NAME"):
|
|
index = param[len("VERIFIC_READ_LIB_NAME"):]
|
|
src_param = "VERIFIC_READ_LIB_SRC" + index
|
|
if src_param in ys_params:
|
|
src_files = []
|
|
for name in ys_params[src_param].split(","):
|
|
for eachfile in args.benchmark_files:
|
|
if name.strip() in eachfile:
|
|
src_files.append(eachfile)
|
|
break
|
|
if not src_files:
|
|
clean_up_and_exit("Failed to locate verific library files")
|
|
lib_files.extend(src_files)
|
|
filename, file_extension = os.path.splitext(src_files[0])
|
|
ys_params["READ_LIBRARY"] += " ".join(["verific -work",
|
|
ys_params[param], ext_to_standard_map[file_extension]] +
|
|
[shlex.quote(eachfile) for eachfile in src_files] + ["\n"])
|
|
standard_to_sources = {}
|
|
for eachfile in args.benchmark_files:
|
|
if eachfile in lib_files:
|
|
continue
|
|
filename, file_extension = os.path.splitext(eachfile)
|
|
if ext_to_standard_map[file_extension] in standard_to_sources:
|
|
standard_to_sources[ext_to_standard_map[file_extension]].append(eachfile)
|
|
else:
|
|
standard_to_sources[ext_to_standard_map[file_extension]] = [eachfile]
|
|
for standard, sources in standard_to_sources.items():
|
|
ys_params["READ_HDL_FILE"] += " ".join(["verific",
|
|
"-L " + ys_params["VERIFIC_SEARCH_LIB"] if "VERIFIC_SEARCH_LIB" in ys_params else "",
|
|
standard, " ".join([shlex.quote(src) for src in sources]), "\n"])
|
|
except:
|
|
logger.exception("Failed to determine design file type")
|
|
clean_up_and_exit("")
|
|
if "YOSYS_CELL_SIM_VERILOG" in ys_params:
|
|
ys_params["READ_HDL_FILE"] += " ".join(["verific",
|
|
ys_params["VERIFIC_VERILOG_STANDARD"],
|
|
ys_params["YOSYS_CELL_SIM_VERILOG"], "\n"])
|
|
if "YOSYS_CELL_SIM_SYSTEMVERILOG" in ys_params:
|
|
ys_params["READ_HDL_FILE"] += " ".join(["verific",
|
|
ys_params["VERIFIC_SYSTEMVERILOG_STANDARD"],
|
|
ys_params["YOSYS_CELL_SIM_SYSTEMVERILOG"], "\n"])
|
|
if "YOSYS_CELL_SIM_VHDL" in ys_params:
|
|
ys_params["READ_HDL_FILE"] += " ".join(["verific",
|
|
ys_params["VERIFIC_VHDL_STANDARD"],
|
|
ys_params["YOSYS_CELL_SIM_VHDL"], "\n"])
|
|
if "YOSYS_BLACKBOX_MODULES" in ys_params:
|
|
ys_params["ADD_BLACKBOX_MODULES"] = ("blackbox " +
|
|
" ".join(["\\" + mod for mod in ys_params["YOSYS_BLACKBOX_MODULES"].split(",")]))
|
|
|
|
ys_params["TOP_MODULE"] = args.top_module
|
|
ys_params["LUT_SIZE"] = lut_size
|
|
ys_params["OUTPUT_BLIF"] = args.top_module+"_yosys_out.blif"
|
|
ys_params["OUTPUT_VERILOG"] = args.top_module+"_output_verilog.v"
|
|
|
|
return ys_params
|
|
|
|
|
|
def run_yosys_with_abc():
|
|
"""
|
|
Execute yosys with ABC and optional blackbox support
|
|
"""
|
|
ys_params = create_yosys_params()
|
|
yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join(
|
|
cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys")
|
|
tmpl = Template(open(yosys_template, encoding='utf-8').read())
|
|
with open("yosys.ys", 'w') as archfile:
|
|
archfile.write(tmpl.safe_substitute(ys_params))
|
|
|
|
run_command("Run yosys", "yosys_output.log",
|
|
[cad_tools["yosys_path"], 'yosys.ys'])
|
|
|
|
|
|
def run_odin2():
|
|
pass
|
|
|
|
|
|
def run_abc_vtr():
|
|
pass
|
|
|
|
|
|
def run_abc_for_standarad():
|
|
pass
|
|
|
|
|
|
def run_ace2():
|
|
if args.black_box_ace:
|
|
with open(args.top_module+'_yosys_out.blif', 'r') as fp:
|
|
blif_lines = fp.readlines()
|
|
|
|
with open(args.top_module+'_bb.blif', 'w') as fp:
|
|
for eachline in blif_lines:
|
|
if ".names" in eachline:
|
|
input_nets = eachline.split()[1:]
|
|
if len(input_nets)-1 > args.K:
|
|
logger.error("One module in blif have more inputs" +
|
|
" than K value")
|
|
# Map CEll to each logic in blif
|
|
map_nets = (input_nets[:-1] + ["unconn"]*args.K)[:args.K]
|
|
map_nets = ["I[%d]=%s" % (indx, eachnet)
|
|
for indx, eachnet in enumerate(map_nets)]
|
|
map_nets += ["O[0]=%s\n" % input_nets[-1]]
|
|
fp.write(".subckt CELL ")
|
|
fp.write(" ".join(map_nets))
|
|
else:
|
|
fp.write(eachline)
|
|
|
|
declar_input = " ".join(["I[%d]" % i for i in range(args.K)])
|
|
model_tmpl = "\n" + \
|
|
".model CELL\n" + \
|
|
".inputs " + declar_input + " \n" + \
|
|
".outputs O[0]\n" + \
|
|
".blackbox\n" + \
|
|
".end\n"
|
|
fp.write(model_tmpl)
|
|
# Prepare ACE run command
|
|
command = [
|
|
"-b", args.top_module +
|
|
('_bb.blif' if args.black_box_ace else "_yosys_out.blif"),
|
|
"-o", args.top_module+"_ace_out.act",
|
|
"-n", args.top_module+"_ace_out.blif",
|
|
"-c", "clk",
|
|
]
|
|
command += ["-d", "%.4f" % args.ace_d] if args.ace_d else [""]
|
|
command += ["-p", "%.4f" % args.ace_d] if args.ace_p else [""]
|
|
try:
|
|
filename = args.top_module + '_ace2_output.txt'
|
|
with open(filename, 'w+') as output:
|
|
process = subprocess.run([cad_tools["ace_path"]] + command,
|
|
check=True,
|
|
stdout=subprocess.PIPE,
|
|
stderr=subprocess.PIPE,
|
|
universal_newlines=True)
|
|
output.write(process.stdout)
|
|
if process.returncode:
|
|
logger.info("ACE2 failed with returncode %d",
|
|
process.returncode)
|
|
raise subprocess.CalledProcessError(0, command)
|
|
except:
|
|
logger.exception("Failed to run ACE2")
|
|
clean_up_and_exit("")
|
|
logger.info("ACE2 output is written in file %s" % filename)
|
|
|
|
|
|
def run_pro_blif_3arg():
|
|
command = [
|
|
"-i", args.top_module+"_ace_out.blif",
|
|
"-o", args.top_module+".blif",
|
|
"-initial_blif", args.top_module+'_yosys_out.blif',
|
|
]
|
|
try:
|
|
filename = args.top_module+'_blif_3args_output.txt'
|
|
with open(filename, 'w+') as output:
|
|
process = subprocess.run(["perl", cad_tools["pro_blif_path"]] +
|
|
command,
|
|
check=True,
|
|
stdout=subprocess.PIPE,
|
|
stderr=subprocess.PIPE,
|
|
universal_newlines=True)
|
|
output.write(process.stdout)
|
|
if process.returncode:
|
|
logger.info("blif_3args script failed with returncode %d",
|
|
process.returncode)
|
|
except:
|
|
logger.exception("Failed to run blif_3args")
|
|
clean_up_and_exit("")
|
|
logger.info("blif_3args output is written in file %s" % filename)
|
|
|
|
|
|
def collect_files_for_vpr():
|
|
# Sanitize provided Benchmark option
|
|
if len(args.benchmark_files) > 1:
|
|
logger.error("Expecting Single Benchmark Blif file.")
|
|
if not os.path.isfile(args.benchmark_files[0] or ""):
|
|
clean_up_and_exit("Provided Blif file not found")
|
|
shutil.copy(args.benchmark_files[0], args.top_module+".blif")
|
|
|
|
# Sanitize provided Activity file option
|
|
if args.power:
|
|
if not os.path.isfile(args.activity_file or ""):
|
|
logger.error("Activity File - %s" % args.activity_file)
|
|
clean_up_and_exit("Provided activity file not found")
|
|
shutil.copy(args.activity_file, args.top_module+"_ace_out.act")
|
|
else:
|
|
if os.path.isfile(args.activity_file):
|
|
shutil.copy(args.activity_file, args.top_module+"_ace_out.act")
|
|
|
|
# Sanitize provided Benchmark option
|
|
if not os.path.isfile(args.base_verilog or ""):
|
|
logger.error("Base Verilog File - %s" % args.base_verilog)
|
|
clean_up_and_exit("Provided base_verilog file not found")
|
|
shutil.copy(args.base_verilog, args.top_module+"_output_verilog.v")
|
|
|
|
|
|
def run_openfpga_shell():
|
|
ExecTime["VPRStart"] = time.time()
|
|
# bench_blif, fixed_chan_width, logfile, route_only=False
|
|
tmpl = Template(open(args.top_module+"_template.openfpga",
|
|
encoding='utf-8').read())
|
|
|
|
path_variables = script_env_vars["PATH"]
|
|
path_variables["TOP_MODULE"] = args.top_module
|
|
path_variables["VPR_ARCH_FILE"] = args.arch_file
|
|
path_variables["OPENFPGA_ARCH_FILE"] = args.openfpga_arch_file
|
|
path_variables["VPR_TESTBENCH_BLIF"] = args.top_module+".blif"
|
|
path_variables["ACTIVITY_FILE"] = args.top_module+"_ace_out.act"
|
|
path_variables["REFERENCE_VERILOG_TESTBENCH"] = args.top_module + \
|
|
"_output_verilog.v"
|
|
|
|
for indx in range(0, len(OpenFPGAArgs), 2):
|
|
tmpVar = OpenFPGAArgs[indx][2:].upper()
|
|
path_variables[tmpVar] = OpenFPGAArgs[indx+1]
|
|
|
|
with open(args.top_module+"_run.openfpga", 'w', encoding='utf-8') as archfile:
|
|
archfile.write(tmpl.safe_substitute(path_variables))
|
|
command = [cad_tools["openfpga_shell_path"], "-batch", "-f",
|
|
args.top_module+"_run.openfpga"]
|
|
run_command("OpenFPGA Shell Run", "openfpgashell.log", command)
|
|
ExecTime["VPREnd"] = time.time()
|
|
extract_vpr_stats("vpr_stdout.log")
|
|
|
|
|
|
def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"):
|
|
section = "DEFAULT_PARSE_RESULT_POWER" if parse_section == "power" \
|
|
else "DEFAULT_PARSE_RESULT_VPR"
|
|
vpr_log = open(logfile).read()
|
|
resultDict = {}
|
|
for name, value in config.items(section):
|
|
reg_string, filt_function = value.split(",")
|
|
match = re.search(reg_string[1:-1], vpr_log)
|
|
if match:
|
|
try:
|
|
if "lambda" in filt_function.strip():
|
|
eval("ParseFunction = "+filt_function.strip())
|
|
extract_val = ParseFunction(**match.groups())
|
|
elif filt_function.strip() == "int":
|
|
extract_val = int(match.group(1))
|
|
elif filt_function.strip() == "float":
|
|
extract_val = float(match.group(1))
|
|
elif filt_function.strip() == "str":
|
|
extract_val = str(match.group(1))
|
|
elif filt_function.strip() == "scientific":
|
|
try:
|
|
mult = {"m": 1E-3, "u": 1E-6, "n": 1E-9,
|
|
"K": 1E-3, "M": 1E-6, "G": 1E-9, }.get(match.group(2)[0], 1)
|
|
except:
|
|
mult = 1
|
|
extract_val = float(match.group(1))*mult
|
|
else:
|
|
extract_val = match.group(1)
|
|
except:
|
|
logger.exception("Filter failed")
|
|
extract_val = "Filter Failed"
|
|
resultDict[name] = extract_val
|
|
|
|
dummyparser = ConfigParser()
|
|
dummyparser.read_dict({"RESULTS": resultDict})
|
|
|
|
with open(r_filename+'.result', 'w') as configfile:
|
|
dummyparser.write(configfile)
|
|
logger.info("%s result extracted in file %s" %
|
|
(parse_section, r_filename+'.result'))
|
|
|
|
|
|
def run_rewrite_verilog():
|
|
# Rewrite the verilog after optimization
|
|
# If there is no template script provided, use a default template
|
|
# If there is a template script provided, replace parameters from configuration
|
|
if not args.ys_rewrite_tmpl:
|
|
script_cmd = [
|
|
"read_blif %s" % args.top_module+".blif",
|
|
"write_verilog %s" % args.top_module+"_output_verilog.v"
|
|
]
|
|
command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)]
|
|
run_command("Yosys", "yosys_rewrite.log", command)
|
|
else:
|
|
# Yosys script parameter mapping
|
|
ys_rewrite_params = create_yosys_params()
|
|
|
|
# Split a series of scripts by delim ';'
|
|
# And execute the scripts serially
|
|
for iteration_idx, curr_rewrite_tmpl in enumerate(args.ys_rewrite_tmpl.split(";")):
|
|
tmpl = Template(open(curr_rewrite_tmpl, encoding='utf-8').read())
|
|
logger.info("Yosys rewrite iteration: " + str(iteration_idx))
|
|
with open("yosys_rewrite_" + str(iteration_idx) + ".ys", 'w') as archfile:
|
|
archfile.write(tmpl.safe_substitute(ys_rewrite_params))
|
|
run_command("Run yosys", "yosys_rewrite_output_" + str(iteration_idx) + ".log",
|
|
[cad_tools["yosys_path"], "yosys_rewrite_" + str(iteration_idx) + ".ys"])
|
|
|
|
|
|
|
|
def run_netlists_verification(exit_if_fail=True):
|
|
ExecTime["VerificationStart"] = time.time()
|
|
compiled_file = "compiled_"+args.top_module
|
|
# include_netlists = args.top_module+"_include_netlists.v"
|
|
tb_top_formal = args.top_module+"_top_formal_verification_random_tb"
|
|
tb_top_autochecked = args.top_module+"_autocheck_top_tb"
|
|
# netlists_path = args.vpr_fpga_verilog_dir_val+"/SRC/"
|
|
|
|
command = [cad_tools["iverilog_path"]]
|
|
command += ["-o", compiled_file]
|
|
|
|
command += ["./SRC/%s_include_netlists.v" % args.top_module]
|
|
command += ["-s"]
|
|
if args.vpr_fpga_verilog_formal_verification_top_netlist:
|
|
command += [tb_top_formal]
|
|
else:
|
|
command += [tb_top_autochecked]
|
|
# TODO: This is NOT flexible!!! We should consider to make the include directory customizable through options
|
|
# Add source directory to the include dir
|
|
command += ["-I", "./SRC"]
|
|
run_command("iverilog_verification", "iverilog_output.txt", command)
|
|
|
|
vvp_command = ["vvp", compiled_file]
|
|
output = run_command("vvp_verification", "vvp_sim_output.txt", vvp_command)
|
|
if "Succeed" in output:
|
|
logger.info("VVP Simulation Successful")
|
|
else:
|
|
logger.error(str(output).split("\n")[-1])
|
|
if exit_if_fail:
|
|
clean_up_and_exit("Failed to run VVP verification")
|
|
ExecTime["VerificationEnd"] = time.time()
|
|
|
|
|
|
def run_command(taskname, logfile, command, exit_if_fail=True):
|
|
logger.info("Launching %s " % taskname)
|
|
with open(logfile, 'w') as output:
|
|
try:
|
|
output.write(" ".join(command)+"\n")
|
|
process = subprocess.run(command,
|
|
stdout=subprocess.PIPE,
|
|
stderr=subprocess.PIPE,
|
|
universal_newlines=True)
|
|
output.write(process.stdout)
|
|
output.write(process.stderr)
|
|
output.write(str(process.returncode))
|
|
if "openfpgashell" in logfile:
|
|
filter_openfpga_output(process.stdout)
|
|
if process.returncode:
|
|
logger.error("%s run failed with returncode %d" %
|
|
(taskname, process.returncode))
|
|
logger.error("command %s" % " ".join(command))
|
|
filter_failed_process_output(process.stderr)
|
|
if exit_if_fail:
|
|
clean_up_and_exit("Failed to run %s task" % taskname)
|
|
except Exception:
|
|
logger.exception("%s failed to execute" % (taskname))
|
|
traceback.print_exc(file=output)
|
|
if exit_if_fail:
|
|
clean_up_and_exit("Failed to run %s task" % taskname)
|
|
logger.info("%s is written in file %s" % (taskname, logfile))
|
|
return process.stdout
|
|
|
|
|
|
def filter_openfpga_output(vpr_output):
|
|
stdout = iter(vpr_output.split("\n"))
|
|
try:
|
|
for i in range(50):
|
|
if "Version:" in next(stdout):
|
|
logger.info("OpenFPGAShell %s %s" %
|
|
(next(stdout), next(stdout)))
|
|
break
|
|
except StopIteration:
|
|
pass
|
|
|
|
|
|
def filter_failed_process_output(vpr_output):
|
|
for line in vpr_output.split("\n"):
|
|
elements_to_log = ["error", "what()"]
|
|
if any(match in line.lower() for match in elements_to_log):
|
|
logger.error("-->>" + line)
|
|
|
|
|
|
if __name__ == "__main__":
|
|
ExecTime["Start"] = time.time()
|
|
# args = parser.parse_args()
|
|
args, OpenFPGAArgs = parser.parse_known_args()
|
|
main()
|