OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p/verilog
tangxifan 6b301d9f44 Merge branch 'dev' into refactoring 2019-10-04 22:47:29 -06:00
..
verilog_api.c start refactoring the switch block verilog generation 2019-09-17 20:40:26 -06:00
verilog_api.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_autocheck_top_testbench.c Big chunk added on the routing part of the explicit mapping 2019-07-02 14:12:42 -06:00
verilog_autocheck_top_testbench.h clean warnings 2019-05-24 16:48:08 -06:00
verilog_compact_netlist.c Revert "Correction on the cb vs sb corrdinator. Does not fix the problem though" 2019-10-03 14:59:04 -06:00
verilog_compact_netlist.h Snapshot of progress 2019-07-02 10:10:48 -06:00
verilog_decoder.c fix 2019-10-01 16:54:16 -06:00
verilog_decoder.h add explicit port mapping for inverters of memory decoders 2019-06-10 17:36:14 -06:00
verilog_decoders.cpp refactored local encoder support for Verilog MUX generation 2019-09-27 23:10:43 -06:00
verilog_decoders.h start refactoring memory decoders 2019-09-13 20:58:55 -06:00
verilog_essential_gates.cpp remove unused ports for Verilog modules 2019-09-11 19:39:59 -06:00
verilog_essential_gates.h plug in module manager 2019-08-23 20:23:41 -06:00
verilog_formal_random_top_testbench.c Update Testbenches to increase accuracy + commented compact routing option until debug 2019-06-26 10:01:12 -06:00
verilog_formal_random_top_testbench.h clean warnings 2019-05-24 16:48:08 -06:00
verilog_formality_autodeck.c Separated Modelsim tcl script generation 2019-09-07 12:36:22 -04:00
verilog_formality_autodeck.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_global.c Finish renaming SCFF to CCFF 2019-09-26 14:04:40 -06:00
verilog_global.h rework on the circuit model ports and start prototyping mux Verilog generation 2019-08-20 15:24:53 -06:00
verilog_include_netlists.c rework on the order of top-level functions 2019-09-13 21:59:52 -06:00
verilog_include_netlists.h add explicit port mapping for inverters of memory decoders 2019-06-10 17:36:14 -06:00
verilog_lut.cpp start adding memory circuit to Switch blocks 2019-09-27 18:08:37 -06:00
verilog_lut.h refactored LUT Verilog generation 2019-09-11 17:04:43 -06:00
verilog_memory.cpp start refactoring instanciation of memory modules 2019-09-29 18:20:56 -06:00
verilog_memory.h Connect CCFFs in a chain in a Verilog module 2019-09-27 20:50:12 -06:00
verilog_modelsim_autodeck.c Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_modelsim_autodeck.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_mux.cpp refactored local encoder support for Verilog MUX generation 2019-09-27 23:10:43 -06:00
verilog_mux.h light modification on Verilog Mux generation and start refactoring memory Verilog generation 2019-09-13 12:22:57 -06:00
verilog_pbtypes.c Fully functional 2019-09-13 16:02:06 -06:00
verilog_pbtypes.h Latest version, not stable yet but close 2019-07-09 08:34:01 -06:00
verilog_primitives.c Fully functional 2019-09-13 16:02:06 -06:00
verilog_primitives.h Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
verilog_report_timing.c Explicit verilog final push 2019-07-16 13:13:30 -06:00
verilog_report_timing.h updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
verilog_routing.c Merge branch 'dev' into refactoring 2019-10-04 22:47:29 -06:00
verilog_routing.h fix 2019-10-01 16:54:16 -06:00
verilog_sdc.c Correction to the explicit Verilog for FPGAs above 2x2 2019-09-13 16:02:06 -06:00
verilog_sdc.h Division between horizontal and vertical analysis 2019-06-25 13:44:41 -06:00
verilog_sdc_pb_types.c Break memories even in the clb sdc 2019-06-16 14:27:29 -06:00
verilog_sdc_pb_types.h clean up warnings in SDC pb_type generator 2019-05-24 15:23:38 -06:00
verilog_submodule_utils.cpp minor tuning on the delay assignment 2019-08-21 23:11:54 -06:00
verilog_submodule_utils.h complete refacotriing the inv and buf part in submodules 2019-08-21 14:54:05 -06:00
verilog_submodules.c fix 2019-10-01 16:54:16 -06:00
verilog_submodules.h develop and plug mux_lib_builder, refactoring the mux submodule generation 2019-08-25 15:33:37 -06:00
verilog_tcl_utils.c Correction to the explicit Verilog for FPGAs above 2x2 2019-09-13 16:02:06 -06:00
verilog_tcl_utils.h Snapshot of progress 2019-07-02 10:10:48 -06:00
verilog_top_netlist_utils.c Explicit verilog passing all tests 2019-10-02 10:22:28 -06:00
verilog_top_netlist_utils.h Latest version explicit 2019-07-11 14:33:56 -06:00
verilog_top_testbench.c Big chunk added on the routing part of the explicit mapping 2019-07-02 14:12:42 -06:00
verilog_top_testbench.h Big chunk added on the routing part of the explicit mapping 2019-07-02 14:12:42 -06:00
verilog_utils.c Explicit verilog passing all tests 2019-10-02 10:22:28 -06:00
verilog_utils.h fix 2019-10-01 16:54:16 -06:00
verilog_verification_top_netlist.c Big chunk added on the routing part of the explicit mapping 2019-07-02 14:12:42 -06:00
verilog_verification_top_netlist.h clean warnings 2019-05-24 16:48:08 -06:00
verilog_wire.cpp refactored user template Verilog generation 2019-09-13 11:41:54 -06:00
verilog_wire.h refactored wire Verilog generation 2019-09-12 20:49:02 -06:00
verilog_writer_utils.cpp simplify the local wire generation for ccffs 2019-09-28 21:36:56 -06:00
verilog_writer_utils.h Refactored Verilog wiring for formal verification ports in Switch Blocks 2019-09-27 13:51:22 -06:00