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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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6a5b50facf
OpenFPGA
/
vpr7_x2p
/
vpr
/
SRC
/
fpga_x2p
History
tangxifan
6a5b50facf
refactored RRAM MUX verilog generation
2019-09-10 20:45:44 -06:00
..
base
refactoring local encoders. Ready to plug in
2019-09-10 15:16:29 -06:00
bitstream
replace spice_models with circuit model in bitstream generator
2019-08-16 16:36:49 -06:00
clb_pin_remap
cleaned unused variables
2019-05-13 14:45:02 -06:00
router
fixed bugs in configure pb_rr_graph and dependence on testbenches
2019-08-16 18:20:30 -06:00
shell
Merge branch 'multimode_clb' of
https://github.com/LNIS-Projects/OpenFPGA
into multimode_clb
2019-05-13 14:45:57 -06:00
spice
added Switch Block SubType and SubFs for tileable rr_graph generation
2019-07-02 10:00:02 -06:00
verilog
refactored RRAM MUX verilog generation
2019-09-10 20:45:44 -06:00