tangxifan a308a13d7c use prefix instead of lib_name when building modules, then use lib_name for standard cell modules		2019-11-05 15:41:59 -07:00
..
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	use prefix instead of lib_name when building modules, then use lib_name for standard cell modules	2019-11-05 15:41:59 -07:00
arch	use prefix instead of lib_name when building modules, then use lib_name for standard cell modules	2019-11-05 15:41:59 -07:00
benchmarks	add explicit port mapping support in testbenches; remove dangling ports in benchmarks	2019-11-02 23:03:47 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Added Modelsim Python Script	2019-11-01 18:20:40 -06:00
scripts	Bug Fix: Corrected read VPR stat filename	2019-11-01 20:51:05 -06:00
tasks	refactoring auto-check top Verilog testbench	2019-11-03 17:41:29 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00