tangxifan a1a5f8cfb6 [test] add new test to valid force clock tap mux routing		2024-11-26 17:36:02 -08:00
..
basic_reg_test.sh	add testcase	2024-11-01 12:15:08 +08:00
basic_reg_yosys_only_test.sh	[test] now use latest python3 of ubuntu 22.04	2024-05-06 11:44:45 -07:00
fpga_bitstream_reg_test.sh	[test] add new test to valid force clock tap mux routing	2024-11-26 17:36:02 -08:00
fpga_sdc_reg_test.sh	[test] now use latest python3 of ubuntu 22.04	2024-05-06 11:44:45 -07:00
fpga_spice_reg_test.sh	[test] now use latest python3 of ubuntu 22.04	2024-05-06 11:44:45 -07:00
fpga_verilog_reg_test.sh	[test] validate mux2 at last stage	2024-09-18 17:40:13 -07:00
iwls_benchmark_reg_test.sh	[test] now use latest python3 of ubuntu 22.04	2024-05-06 11:44:45 -07:00
micro_benchmark_reg_test.sh	[test] now use latest python3 of ubuntu 22.04	2024-05-06 11:44:45 -07:00
quicklogic_reg_test.sh	[test] now use latest python3 of ubuntu 22.04	2024-05-06 11:44:45 -07:00
tcl_reg_test.sh	[script] enable eval mode in tcl reg test	2022-12-02 12:07:27 -08:00
vtr_benchmark_reg_test.sh	[test] now use latest python3 of ubuntu 22.04	2024-05-06 11:44:45 -07:00