37 lines
1.4 KiB
C++
37 lines
1.4 KiB
C++
#ifndef VERILOG_SUBMODULE_UTILS_H
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#define VERILOG_SUBMODULE_UTILS_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <fstream>
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#include <string>
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#include "module_manager.h"
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#include "circuit_library.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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void print_verilog_submodule_timing(std::fstream& fp,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model);
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void print_verilog_submodule_signal_init(std::fstream& fp,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model);
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void add_user_defined_verilog_modules(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib);
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void print_verilog_submodule_templates(const ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const std::string& submodule_dir);
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} /* end namespace openfpga */
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#endif
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