77 lines
2.9 KiB
C++
77 lines
2.9 KiB
C++
#ifndef BUILD_TOP_MODULE_MEMORY_H
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#define BUILD_TOP_MODULE_MEMORY_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <map>
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#include <vector>
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#include "build_top_module_memory_utils.h"
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#include "circuit_library.h"
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#include "circuit_types.h"
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#include "config_protocol.h"
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#include "decoder_library.h"
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#include "device_grid.h"
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#include "device_rr_gsb.h"
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#include "fabric_key.h"
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#include "memory_bank_shift_register_banks.h"
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#include "module_manager.h"
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#include "rr_graph_view.h"
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#include "vtr_ndmatrix.h"
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#include "vtr_vector.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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void organize_top_module_memory_modules(
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ModuleManager& module_manager, const ModuleId& top_module,
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const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
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const CircuitModelId& sram_model, const DeviceGrid& grids,
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const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids,
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const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph,
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const vtr::Matrix<size_t>& sb_instance_ids,
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const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
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const bool& compact_routing_hierarchy);
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void build_top_module_configurable_regions(
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ModuleManager& module_manager, const ModuleId& top_module,
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const ConfigProtocol& config_protocol);
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void shuffle_top_module_configurable_children(
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ModuleManager& module_manager, const ModuleId& top_module,
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const ConfigProtocol& config_protocol);
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int load_top_module_memory_modules_from_fabric_key(
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ModuleManager& module_manager, const ModuleId& top_module,
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const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
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const FabricKey& fabric_key);
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TopModuleNumConfigBits find_top_module_regional_num_config_bit(
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const ModuleManager& module_manager, const ModuleId& top_module,
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const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model,
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const e_config_protocol_type& config_protocol_type);
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void add_top_module_sram_ports(
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ModuleManager& module_manager, const ModuleId& module_id,
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const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model,
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const ConfigProtocol& config_protocol,
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const MemoryBankShiftRegisterBanks& blwl_sr_banks,
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const TopModuleNumConfigBits& num_config_bits);
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void add_top_module_nets_memory_config_bus(
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ModuleManager& module_manager, DecoderLibrary& decoder_lib,
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MemoryBankShiftRegisterBanks& blwl_sr_banks, const ModuleId& parent_module,
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const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
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const e_circuit_model_design_tech& mem_tech,
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const TopModuleNumConfigBits& num_config_bits);
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} /* end namespace openfpga */
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#endif
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